return rowStride * height * depth;
}
-unsigned get_texture_image_row_stride(radeonContextPtr rmesa, gl_format format, unsigned width, unsigned tiling)
+unsigned get_texture_image_row_stride(radeonContextPtr rmesa, gl_format format, unsigned width, unsigned tiling, GLuint target)
{
if (_mesa_is_format_compressed(format)) {
return get_aligned_compressed_row_stride(format, width, rmesa->texture_compressed_row_align);
} else {
unsigned row_align;
- if (!_mesa_is_pow_two(width)) {
+ if (!_mesa_is_pow_two(width) || target == GL_TEXTURE_RECTANGLE) {
row_align = rmesa->texture_rect_row_align - 1;
} else if (tiling) {
unsigned tileWidth, tileHeight;
height = _mesa_next_pow_two_32(lvl->height);
- lvl->rowstride = get_texture_image_row_stride(rmesa, mt->mesaFormat, lvl->width, mt->tilebits);
- lvl->size = get_texture_image_size(mt->mesaFormat, lvl->rowstride, lvl->height, lvl->depth, mt->tilebits);
+ lvl->rowstride = get_texture_image_row_stride(rmesa, mt->mesaFormat, lvl->width, mt->tilebits, mt->target);
+ lvl->size = get_texture_image_size(mt->mesaFormat, lvl->rowstride, height, lvl->depth, mt->tilebits);
assert(lvl->size > 0);
}
-static void calculate_miptree_layout_r100(radeonContextPtr rmesa, radeon_mipmap_tree *mt)
+static void calculate_miptree_layout(radeonContextPtr rmesa, radeon_mipmap_tree *mt)
{
GLuint curOffset, i, face, level;
__func__, rmesa, mt, mt->totalsize);
}
-static void calculate_miptree_layout_r300(radeonContextPtr rmesa, radeon_mipmap_tree *mt)
-{
- GLuint curOffset, i, level;
-
- assert(mt->numLevels <= rmesa->glCtx->Const.MaxTextureLevels);
-
- curOffset = 0;
- for(i = 0, level = mt->baseLevel; i < mt->numLevels; i++, level++) {
- GLuint face;
-
- mt->levels[level].valid = 1;
- mt->levels[level].width = minify(mt->width0, i);
- mt->levels[level].height = minify(mt->height0, i);
- mt->levels[level].depth = minify(mt->depth0, i);
-
- for(face = 0; face < mt->faces; face++)
- compute_tex_image_offset(rmesa, mt, face, level, &curOffset);
- /* r600 cube levels seems to be aligned to 8 faces but
- * we have separate register for 1'st level offset so add
- * 2 image alignment after 1'st mip level */
- if(rmesa->radeonScreen->chip_family >= CHIP_FAMILY_R600 &&
- mt->target == GL_TEXTURE_CUBE_MAP && level >= 1)
- curOffset += 2 * mt->levels[level].size;
- }
-
- /* Note the required size in memory */
- mt->totalsize = (curOffset + RADEON_OFFSET_MASK) & ~RADEON_OFFSET_MASK;
-
- radeon_print(RADEON_TEXTURE, RADEON_TRACE,
- "%s(%p, %p) total size %d\n",
- __func__, rmesa, mt, mt->totalsize);
-}
-
/**
* Create a new mipmap tree, calculate its layout and allocate memory.
*/
mt->depth0 = depth0;
mt->tilebits = tilebits;
- if (rmesa->radeonScreen->chip_family >= CHIP_FAMILY_R300)
- calculate_miptree_layout_r300(rmesa, mt);
- else
- calculate_miptree_layout_r100(rmesa, mt);
+ calculate_miptree_layout(rmesa, mt);
mt->bo = radeon_bo_open(rmesa->radeonScreen->bom,
0, mt->totalsize, 1024,
case GL_TEXTURE_2D:
case GL_TEXTURE_3D:
case GL_TEXTURE_CUBE_MAP:
- if (tObj->MinFilter == GL_NEAREST || tObj->MinFilter == GL_LINEAR) {
+ if (tObj->Sampler.MinFilter == GL_NEAREST || tObj->Sampler.MinFilter == GL_LINEAR) {
/* GL_NEAREST and GL_LINEAR only care about GL_TEXTURE_BASE_LEVEL.
*/
minLod = maxLod = tObj->BaseLevel;
} else {
- minLod = tObj->BaseLevel + (GLint)(tObj->MinLod);
+ minLod = tObj->BaseLevel + (GLint)(tObj->Sampler.MinLod);
minLod = MAX2(minLod, tObj->BaseLevel);
minLod = MIN2(minLod, tObj->MaxLevel);
- maxLod = tObj->BaseLevel + (GLint)(tObj->MaxLod + 0.5);
+ maxLod = tObj->BaseLevel + (GLint)(tObj->Sampler.MaxLod + 0.5);
maxLod = MIN2(maxLod, tObj->MaxLevel);
maxLod = MIN2(maxLod, tObj->Image[0][minLod]->MaxLog2 + minLod);
maxLod = MAX2(maxLod, minLod); /* need at least one level */
assert(image->mt != mt);
assert(dstlvl->valid);
- assert(dstlvl->width == image->base.Width);
- assert(dstlvl->height == image->base.Height);
- assert(dstlvl->depth == image->base.Depth);
+ assert(dstlvl->width == image->base.Base.Width);
+ assert(dstlvl->height == image->base.Base.Height);
+ assert(dstlvl->depth == image->base.Base.Depth);
radeon_print(RADEON_TEXTURE, RADEON_VERBOSE,
"%s miptree %p, image %p, face %d, level %d.\n",
* In fact, that memcpy() could be done by the hardware in many
* cases, provided that we have a proper memory manager.
*/
- assert(mt->mesaFormat == image->base.TexFormat);
+ assert(mt->mesaFormat == image->base.Base.TexFormat);
- radeon_mipmap_level *srclvl = &image->mt->levels[image->mtlevel];
+ radeon_mipmap_level *srclvl = &image->mt->levels[image->base.Base.Level];
- assert(image->mtlevel == level);
+ assert(image->base.Base.Level == level);
assert(srclvl->size == dstlvl->size);
assert(srclvl->rowstride == dstlvl->rowstride);
radeon_print(RADEON_FALLBACKS, RADEON_IMPORTANT,
"%s Trying to map texture in sowftware fallback.\n",
__func__);
- const uint32_t srcrowstride = _mesa_format_row_stride(image->base.TexFormat, image->base.Width);
- uint32_t rows = image->base.Height * image->base.Depth;
+ const uint32_t srcrowstride = _mesa_format_row_stride(image->base.Base.TexFormat, image->base.Base.Width);
+ uint32_t rows = image->base.Base.Height * image->base.Base.Depth;
- if (_mesa_is_format_compressed(image->base.TexFormat)) {
+ if (_mesa_is_format_compressed(image->base.Base.TexFormat)) {
uint32_t blockWidth, blockHeight;
- _mesa_get_format_block_size(image->base.TexFormat, &blockWidth, &blockHeight);
+ _mesa_get_format_block_size(image->base.Base.TexFormat, &blockWidth, &blockHeight);
rows = (rows + blockHeight - 1) / blockHeight;
}
copy_rows(dest, dstlvl->rowstride, image->base.Data, srcrowstride,
rows, srcrowstride);
- _mesa_free_texmemory(image->base.Data);
+ _mesa_align_free(image->base.Data);
image->base.Data = 0;
}
radeon_bo_unmap(mt->bo);
radeon_miptree_reference(mt, &image->mt);
- image->mtface = face;
- image->mtlevel = level;
}
/**
unsigned mtCount = 0;
unsigned maxMtIndex = 0;
radeon_mipmap_tree *tmp;
+ unsigned int level;
+ int i;
- for (unsigned level = firstLevel; level <= lastLevel; ++level) {
+ for (level = firstLevel; level <= lastLevel; ++level) {
radeon_texture_image *img = get_radeon_texture_image(texObj->base.Image[0][level]);
unsigned found = 0;
// TODO: why this hack??
if (!img->mt)
continue;
- for (int i = 0; i < mtCount; ++i) {
+ for (i = 0; i < mtCount; ++i) {
if (mts[i] == img->mt) {
found = 1;
- mtSizes[i] += img->mt->levels[img->mtlevel].size;
+ mtSizes[i] += img->mt->levels[img->base.Base.Level].size;
break;
}
}
if (!found && radeon_miptree_matches_texture(img->mt, &texObj->base)) {
- mtSizes[mtCount] = img->mt->levels[img->mtlevel].size;
+ mtSizes[mtCount] = img->mt->levels[img->base.Base.Level].size;
mts[mtCount] = img->mt;
mtCount++;
}
return NULL;
}
- for (int i = 1; i < mtCount; ++i) {
+ for (i = 1; i < mtCount; ++i) {
if (mtSizes[i] > mtSizes[maxMtIndex]) {
maxMtIndex = i;
}
* If individual images are stored in different mipmap trees
* use the mipmap tree that has the most of the correct data.
*/
-int radeon_validate_texture_miptree(GLcontext * ctx, struct gl_texture_object *texObj)
+int radeon_validate_texture_miptree(struct gl_context * ctx, struct gl_texture_object *texObj)
{
radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
radeonTexObj *t = radeon_tex_obj(texObj);
__FUNCTION__, texObj ,t->minLod, t->maxLod);
radeon_mipmap_tree *dst_miptree;
- dst_miptree = get_biggest_matching_miptree(t, t->minLod, t->maxLod);
+ dst_miptree = get_biggest_matching_miptree(t, t->base.BaseLevel, t->base.MaxLevel);
+ radeon_miptree_unreference(&t->mt);
if (!dst_miptree) {
- radeon_miptree_unreference(&t->mt);
radeon_try_alloc_miptree(rmesa, t);
- dst_miptree = t->mt;
radeon_print(RADEON_TEXTURE, RADEON_NORMAL,
"%s: No matching miptree found, allocated new one %p\n",
__FUNCTION__, t->mt);
} else {
+ radeon_miptree_reference(dst_miptree, &t->mt);
radeon_print(RADEON_TEXTURE, RADEON_NORMAL,
"%s: Using miptree %p\n", __FUNCTION__, t->mt);
}
"Checking image level %d, face %d, mt %p ... ",
level, face, img->mt);
- if (img->mt != dst_miptree) {
+ if (img->mt != t->mt) {
radeon_print(RADEON_TEXTURE, RADEON_TRACE,
"MIGRATING\n");
if (src_bo && radeon_bo_is_referenced_by_cs(src_bo, rmesa->cmdbuf.cs)) {
radeon_firevertices(rmesa);
}
- migrate_image_to_miptree(dst_miptree, img, face, level);
+ migrate_image_to_miptree(t->mt, img, face, level);
} else
radeon_print(RADEON_TEXTURE, RADEON_TRACE, "OK\n");
}
projects / mesa.git / blobdiff