intel: Use separate stencil whenever possible

[mesa.git] / src / mesa / drivers / dri / radeon / radeon_mipmap_tree.c

diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
index a9901382f84f53f723a73c945979cbb80116f1e3..05daf1cec4344b33b3210ce3669308b534c2149b 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
@@ -96,14 +96,14 @@ unsigned get_texture_image_size(
        return rowStride * height * depth;
 }
 
-unsigned get_texture_image_row_stride(radeonContextPtr rmesa, gl_format format, unsigned width, unsigned tiling)
+unsigned get_texture_image_row_stride(radeonContextPtr rmesa, gl_format format, unsigned width, unsigned tiling, GLuint target)
 {
        if (_mesa_is_format_compressed(format)) {
                return get_aligned_compressed_row_stride(format, width, rmesa->texture_compressed_row_align);
        } else {
                unsigned row_align;
 
-               if (!_mesa_is_pow_two(width)) {
+               if (!_mesa_is_pow_two(width) || target == GL_TEXTURE_RECTANGLE) {
                        row_align = rmesa->texture_rect_row_align - 1;
                } else if (tiling) {
                        unsigned tileWidth, tileHeight;
@@ -132,7 +132,7 @@ static void compute_tex_image_offset(radeonContextPtr rmesa, radeon_mipmap_tree
 
        height = _mesa_next_pow_two_32(lvl->height);
 
-       lvl->rowstride = get_texture_image_row_stride(rmesa, mt->mesaFormat, lvl->width, mt->tilebits);
+       lvl->rowstride = get_texture_image_row_stride(rmesa, mt->mesaFormat, lvl->width, mt->tilebits, mt->target);
        lvl->size = get_texture_image_size(mt->mesaFormat, lvl->rowstride, height, lvl->depth, mt->tilebits);
 
        assert(lvl->size > 0);
@@ -156,7 +156,7 @@ static GLuint minify(GLuint size, GLuint levels)
 }
 
 
-static void calculate_miptree_layout_r100(radeonContextPtr rmesa, radeon_mipmap_tree *mt)
+static void calculate_miptree_layout(radeonContextPtr rmesa, radeon_mipmap_tree *mt)
 {
        GLuint curOffset, i, face, level;
 
@@ -182,39 +182,6 @@ static void calculate_miptree_layout_r100(radeonContextPtr rmesa, radeon_mipmap_
                        __func__, rmesa, mt, mt->totalsize);
 }
 
-static void calculate_miptree_layout_r300(radeonContextPtr rmesa, radeon_mipmap_tree *mt)
-{
-       GLuint curOffset, i, level;
-
-       assert(mt->numLevels <= rmesa->glCtx->Const.MaxTextureLevels);
-
-       curOffset = 0;
-       for(i = 0, level = mt->baseLevel; i < mt->numLevels; i++, level++) {
-               GLuint face;
-
-               mt->levels[level].valid = 1;
-               mt->levels[level].width = minify(mt->width0, i);
-               mt->levels[level].height = minify(mt->height0, i);
-               mt->levels[level].depth = minify(mt->depth0, i);
-
-               for(face = 0; face < mt->faces; face++)
-                       compute_tex_image_offset(rmesa, mt, face, level, &curOffset);
-               /* from r700? cube levels seems to be aligned to 8 faces,
-                * as we have separate register for 1'st level offset add
-                * 2 image alignment after 1'st mip level */
-               if(rmesa->radeonScreen->chip_family >= CHIP_FAMILY_RV770 &&
-                  mt->target == GL_TEXTURE_CUBE_MAP && level >= 1)
-                       curOffset += 2 * mt->levels[level].size;
-       }
-
-       /* Note the required size in memory */
-       mt->totalsize = (curOffset + RADEON_OFFSET_MASK) & ~RADEON_OFFSET_MASK;
-
-       radeon_print(RADEON_TEXTURE, RADEON_TRACE,
-                       "%s(%p, %p) total size %d\n",
-                       __func__, rmesa, mt, mt->totalsize);
-}
-
 /**
  * Create a new mipmap tree, calculate its layout and allocate memory.
  */
@@ -239,10 +206,7 @@ static radeon_mipmap_tree* radeon_miptree_create(radeonContextPtr rmesa,
        mt->depth0 = depth0;
        mt->tilebits = tilebits;
 
-       if (rmesa->radeonScreen->chip_family >= CHIP_FAMILY_R300)
-               calculate_miptree_layout_r300(rmesa, mt);
-       else
-               calculate_miptree_layout_r100(rmesa, mt);
+       calculate_miptree_layout(rmesa, mt);
 
        mt->bo = radeon_bo_open(rmesa->radeonScreen->bom,
                             0, mt->totalsize, 1024,