#include <errno.h>
#include <unistd.h>
-#include "main/simple_list.h"
#include "main/teximage.h"
#include "main/texobj.h"
#include "main/enums.h"
+#include "util/u_memory.h"
#include "radeon_texture.h"
#include "radeon_tile.h"
static unsigned get_aligned_compressed_row_stride(
- gl_format format,
+ mesa_format format,
unsigned width,
unsigned minStride)
{
}
unsigned get_texture_image_size(
- gl_format format,
+ mesa_format format,
unsigned rowStride,
unsigned height,
unsigned depth,
return rowStride * height * depth;
}
-unsigned get_texture_image_row_stride(radeonContextPtr rmesa, gl_format format, unsigned width, unsigned tiling, GLuint target)
+unsigned get_texture_image_row_stride(radeonContextPtr rmesa, mesa_format format, unsigned width, unsigned tiling, GLuint target)
{
if (_mesa_is_format_compressed(format)) {
return get_aligned_compressed_row_stride(format, width, rmesa->texture_compressed_row_align);
} else {
unsigned row_align;
- if (!_mesa_is_pow_two(width) || target == GL_TEXTURE_RECTANGLE) {
+ if (!util_is_power_of_two_or_zero(width) || target == GL_TEXTURE_RECTANGLE) {
row_align = rmesa->texture_rect_row_align - 1;
} else if (tiling) {
unsigned tileWidth, tileHeight;
radeon_mipmap_level *lvl = &mt->levels[level];
GLuint height;
- height = _mesa_next_pow_two_32(lvl->height);
+ height = util_next_power_of_two(lvl->height);
lvl->rowstride = get_texture_image_row_stride(rmesa, mt->mesaFormat, lvl->width, mt->tilebits, mt->target);
lvl->size = get_texture_image_size(mt->mesaFormat, lvl->rowstride, height, lvl->depth, mt->tilebits);
lvl->rowstride, lvl->width, height, lvl->faces[face].offset);
}
-static GLuint minify(GLuint size, GLuint levels)
-{
- size = size >> levels;
- if (size < 1)
- size = 1;
- return size;
-}
-
-
static void calculate_miptree_layout(radeonContextPtr rmesa, radeon_mipmap_tree *mt)
{
GLuint curOffset, i, face, level;
- assert(mt->numLevels <= rmesa->glCtx->Const.MaxTextureLevels);
+ assert(1 << (mt->numLevels - 1) <= rmesa->glCtx.Const.MaxTextureSize);
curOffset = 0;
for(face = 0; face < mt->faces; face++) {
* Create a new mipmap tree, calculate its layout and allocate memory.
*/
radeon_mipmap_tree* radeon_miptree_create(radeonContextPtr rmesa,
- GLenum target, gl_format mesaFormat, GLuint baseLevel, GLuint numLevels,
+ GLenum target, mesa_format mesaFormat, GLuint baseLevel, GLuint numLevels,
GLuint width0, GLuint height0, GLuint depth0, GLuint tilebits)
{
radeon_mipmap_tree *mt = CALLOC_STRUCT(_radeon_mipmap_tree);
mt->mesaFormat = mesaFormat;
mt->refcount = 1;
mt->target = target;
- mt->faces = (target == GL_TEXTURE_CUBE_MAP) ? 6 : 1;
+ mt->faces = _mesa_num_tex_faces(target);
mt->baseLevel = baseLevel;
mt->numLevels = numLevels;
mt->width0 = width0;
* @param[out] pminLod minimal LOD
* @param[out] pmaxLod maximal LOD
*/
-static void calculate_min_max_lod(struct gl_texture_object *tObj,
+static void calculate_min_max_lod(struct gl_sampler_object *samp, struct gl_texture_object *tObj,
unsigned *pminLod, unsigned *pmaxLod)
{
int minLod, maxLod;
case GL_TEXTURE_2D:
case GL_TEXTURE_3D:
case GL_TEXTURE_CUBE_MAP:
- if (tObj->Sampler.MinFilter == GL_NEAREST || tObj->Sampler.MinFilter == GL_LINEAR) {
+ if (samp->MinFilter == GL_NEAREST || samp->MinFilter == GL_LINEAR) {
/* GL_NEAREST and GL_LINEAR only care about GL_TEXTURE_BASE_LEVEL.
*/
minLod = maxLod = tObj->BaseLevel;
} else {
- minLod = tObj->BaseLevel + (GLint)(tObj->Sampler.MinLod);
+ minLod = tObj->BaseLevel + (GLint)(samp->MinLod);
minLod = MAX2(minLod, tObj->BaseLevel);
minLod = MIN2(minLod, tObj->MaxLevel);
- maxLod = tObj->BaseLevel + (GLint)(tObj->Sampler.MaxLod + 0.5);
+ maxLod = tObj->BaseLevel + (GLint)(samp->MaxLod + 0.5);
maxLod = MIN2(maxLod, tObj->MaxLevel);
- maxLod = MIN2(maxLod, tObj->Image[0][minLod]->MaxLog2 + minLod);
+ maxLod = MIN2(maxLod, tObj->Image[0][minLod]->MaxNumLevels - 1 + minLod);
maxLod = MAX2(maxLod, minLod); /* need at least one level */
}
break;
radeon_print(RADEON_TEXTURE, RADEON_TRACE,
"%s(%p) target %s, min %d, max %d.\n",
__func__, tObj,
- _mesa_lookup_enum_by_nr(tObj->Target),
+ _mesa_enum_to_string(tObj->Target),
minLod, maxLod);
/* save these values */
mtBaseLevel = &mt->levels[texObj->BaseLevel - mt->baseLevel];
firstImage = texObj->Image[0][texObj->BaseLevel];
- numLevels = MIN2(texObj->_MaxLevel - texObj->BaseLevel + 1, firstImage->MaxLog2 + 1);
+ numLevels = MIN2(texObj->_MaxLevel - texObj->BaseLevel + 1, firstImage->MaxNumLevels);
if (radeon_is_debug_enabled(RADEON_TEXTURE,RADEON_TRACE)) {
fprintf(stderr, "Checking if miptree %p matches texObj %p\n", mt, texObj);
}
- numLevels = MIN2(texObj->MaxLevel - texObj->BaseLevel + 1, texImg->MaxLog2 + 1);
+ numLevels = MIN2(texObj->MaxLevel - texObj->BaseLevel + 1, texImg->MaxNumLevels);
t->mt = radeon_miptree_create(rmesa, t->base.Target,
texImg->TexFormat, texObj->BaseLevel,
radeon_bo_unmap(image->mt->bo);
radeon_miptree_unreference(&image->mt);
- } else if (image->base.Map) {
- /* This condition should be removed, it's here to workaround
- * a segfault when mapping textures during software fallbacks.
- */
- radeon_print(RADEON_FALLBACKS, RADEON_IMPORTANT,
- "%s Trying to map texture in software fallback.\n",
- __func__);
- const uint32_t srcrowstride = _mesa_format_row_stride(image->base.Base.TexFormat, image->base.Base.Width);
- uint32_t rows = image->base.Base.Height * image->base.Base.Depth;
-
- if (_mesa_is_format_compressed(image->base.Base.TexFormat)) {
- uint32_t blockWidth, blockHeight;
- _mesa_get_format_block_size(image->base.Base.TexFormat, &blockWidth, &blockHeight);
- rows = (rows + blockHeight - 1) / blockHeight;
- }
-
- copy_rows(dest, dstlvl->rowstride, image->base.Map, srcrowstride,
- rows, srcrowstride);
-
- _mesa_align_free(image->base.Map);
- image->base.Map = 0;
}
radeon_bo_unmap(mt->bo);
* If individual images are stored in different mipmap trees
* use the mipmap tree that has the most of the correct data.
*/
-int radeon_validate_texture_miptree(struct gl_context * ctx, struct gl_texture_object *texObj)
+int radeon_validate_texture_miptree(struct gl_context * ctx,
+ struct gl_sampler_object *samp,
+ struct gl_texture_object *texObj)
{
radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
radeonTexObj *t = radeon_tex_obj(texObj);
radeon_mipmap_tree *dst_miptree;
- if (t->validated || t->image_override) {
+ if (samp == &texObj->Sampler && (t->validated || t->image_override)) {
return GL_TRUE;
}
- calculate_min_max_lod(&t->base, &t->minLod, &t->maxLod);
+ calculate_min_max_lod(samp, &t->base, &t->minLod, &t->maxLod);
radeon_print(RADEON_TEXTURE, RADEON_NORMAL,
"%s: Validating texture %p now, minLod = %d, maxLod = %d\n",
- __FUNCTION__, texObj ,t->minLod, t->maxLod);
+ __func__, texObj ,t->minLod, t->maxLod);
dst_miptree = get_biggest_matching_miptree(t, t->base.BaseLevel, t->base._MaxLevel);
radeon_try_alloc_miptree(rmesa, t);
radeon_print(RADEON_TEXTURE, RADEON_NORMAL,
"%s: No matching miptree found, allocated new one %p\n",
- __FUNCTION__, t->mt);
+ __func__, t->mt);
} else {
radeon_miptree_reference(dst_miptree, &t->mt);
radeon_print(RADEON_TEXTURE, RADEON_NORMAL,
- "%s: Using miptree %p\n", __FUNCTION__, t->mt);
+ "%s: Using miptree %p\n", __func__, t->mt);
}
- const unsigned faces = texObj->Target == GL_TEXTURE_CUBE_MAP ? 6 : 1;
+ const unsigned faces = _mesa_num_tex_faces(texObj->Target);
unsigned face, level;
radeon_texture_image *img;
/* Validate only the levels that will actually be used during rendering */
projects / mesa.git / blobdiff