mesa: add bool param to _mesa_free_context_data

[mesa.git] / src / mesa / drivers / dri / radeon / radeon_mipmap_tree.c

diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
index ebf6a194cc974421f5079920f88f0e6e53a4c727..09ccc5c6a12ec5a6d519b778f9abb61633ffd17a 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
@@ -31,15 +31,15 @@
 #include <errno.h>
 #include <unistd.h>
 
-#include "main/simple_list.h"
 #include "main/teximage.h"
 #include "main/texobj.h"
 #include "main/enums.h"
+#include "util/u_memory.h"
 #include "radeon_texture.h"
 #include "radeon_tile.h"
 
 static unsigned get_aligned_compressed_row_stride(
-               gl_format format,
+               mesa_format format,
                unsigned width,
                unsigned minStride)
 {
@@ -71,7 +71,7 @@ static unsigned get_aligned_compressed_row_stride(
 }
 
 unsigned get_texture_image_size(
-               gl_format format,
+               mesa_format format,
                unsigned rowStride,
                unsigned height,
                unsigned depth,
@@ -96,14 +96,14 @@ unsigned get_texture_image_size(
        return rowStride * height * depth;
 }
 
-unsigned get_texture_image_row_stride(radeonContextPtr rmesa, gl_format format, unsigned width, unsigned tiling, GLuint target)
+unsigned get_texture_image_row_stride(radeonContextPtr rmesa, mesa_format format, unsigned width, unsigned tiling, GLuint target)
 {
        if (_mesa_is_format_compressed(format)) {
                return get_aligned_compressed_row_stride(format, width, rmesa->texture_compressed_row_align);
        } else {
                unsigned row_align;
 
-               if (!_mesa_is_pow_two(width) || target == GL_TEXTURE_RECTANGLE) {
+               if (!util_is_power_of_two_or_zero(width) || target == GL_TEXTURE_RECTANGLE) {
                        row_align = rmesa->texture_rect_row_align - 1;
                } else if (tiling) {
                        unsigned tileWidth, tileHeight;
@@ -130,7 +130,7 @@ static void compute_tex_image_offset(radeonContextPtr rmesa, radeon_mipmap_tree
        radeon_mipmap_level *lvl = &mt->levels[level];
        GLuint height;
 
-       height = _mesa_next_pow_two_32(lvl->height);
+       height = util_next_power_of_two(lvl->height);
 
        lvl->rowstride = get_texture_image_row_stride(rmesa, mt->mesaFormat, lvl->width, mt->tilebits, mt->target);
        lvl->size = get_texture_image_size(mt->mesaFormat, lvl->rowstride, height, lvl->depth, mt->tilebits);
@@ -151,7 +151,7 @@ static void calculate_miptree_layout(radeonContextPtr rmesa, radeon_mipmap_tree
 {
        GLuint curOffset, i, face, level;
 
-       assert(mt->numLevels <= rmesa->glCtx.Const.MaxTextureLevels);
+       assert(1 << (mt->numLevels - 1) <= rmesa->glCtx.Const.MaxTextureSize);
 
        curOffset = 0;
        for(face = 0; face < mt->faces; face++) {
@@ -177,7 +177,7 @@ static void calculate_miptree_layout(radeonContextPtr rmesa, radeon_mipmap_tree
  * Create a new mipmap tree, calculate its layout and allocate memory.
  */
 radeon_mipmap_tree* radeon_miptree_create(radeonContextPtr rmesa,
-                                         GLenum target, gl_format mesaFormat, GLuint baseLevel, GLuint numLevels,
+                                         GLenum target, mesa_format mesaFormat, GLuint baseLevel, GLuint numLevels,
                                          GLuint width0, GLuint height0, GLuint depth0, GLuint tilebits)
 {
        radeon_mipmap_tree *mt = CALLOC_STRUCT(_radeon_mipmap_tree);
@@ -276,7 +276,7 @@ static void calculate_min_max_lod(struct gl_sampler_object *samp, struct gl_text
        radeon_print(RADEON_TEXTURE, RADEON_TRACE,
                        "%s(%p) target %s, min %d, max %d.\n",
                        __func__, tObj,
-                       _mesa_lookup_enum_by_nr(tObj->Target),
+                       _mesa_enum_to_string(tObj->Target),
                        minLod, maxLod);
 
        /* save these values */
@@ -431,27 +431,6 @@ static void migrate_image_to_miptree(radeon_mipmap_tree *mt,
                radeon_bo_unmap(image->mt->bo);
 
                radeon_miptree_unreference(&image->mt);
-       } else if (image->base.Map) {
-               /* This condition should be removed, it's here to workaround
-                * a segfault when mapping textures during software fallbacks.
-                */
-               radeon_print(RADEON_FALLBACKS, RADEON_IMPORTANT,
-                               "%s Trying to map texture in software fallback.\n",
-                               __func__);
-               const uint32_t srcrowstride = _mesa_format_row_stride(image->base.Base.TexFormat, image->base.Base.Width);
-               uint32_t rows = image->base.Base.Height * image->base.Base.Depth;
-
-               if (_mesa_is_format_compressed(image->base.Base.TexFormat)) {
-                       uint32_t blockWidth, blockHeight;
-                       _mesa_get_format_block_size(image->base.Base.TexFormat, &blockWidth, &blockHeight);
-                       rows = (rows + blockHeight - 1) / blockHeight;
-               }
-
-               copy_rows(dest, dstlvl->rowstride, image->base.Map, srcrowstride,
-                                 rows, srcrowstride);
-
-               _mesa_align_free(image->base.Map);
-               image->base.Map = 0;
        }
 
        radeon_bo_unmap(mt->bo);
@@ -543,7 +522,7 @@ int radeon_validate_texture_miptree(struct gl_context * ctx,
 
        radeon_print(RADEON_TEXTURE, RADEON_NORMAL,
                        "%s: Validating texture %p now, minLod = %d, maxLod = %d\n",
-                       __FUNCTION__, texObj ,t->minLod, t->maxLod);
+                       __func__, texObj ,t->minLod, t->maxLod);
 
        dst_miptree = get_biggest_matching_miptree(t, t->base.BaseLevel, t->base._MaxLevel);
 
@@ -552,12 +531,12 @@ int radeon_validate_texture_miptree(struct gl_context * ctx,
                radeon_try_alloc_miptree(rmesa, t);
                radeon_print(RADEON_TEXTURE, RADEON_NORMAL,
                        "%s: No matching miptree found, allocated new one %p\n",
-                       __FUNCTION__, t->mt);
+                       __func__, t->mt);
 
        } else {
                radeon_miptree_reference(dst_miptree, &t->mt);
                radeon_print(RADEON_TEXTURE, RADEON_NORMAL,
-                       "%s: Using miptree %p\n", __FUNCTION__, t->mt);
+                       "%s: Using miptree %p\n", __func__, t->mt);
        }
 
        const unsigned faces = _mesa_num_tex_faces(texObj->Target);