replace _mesa_next_pow_two_* with util_next_power_of_two_*
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_mipmap_tree.c
index 19e62969e5c1cf0b22afe171b0bbf0231e8ffbee..979739d62bef74bef31f5c887f13202c00d7cbf8 100644 (file)
@@ -102,7 +102,7 @@ unsigned get_texture_image_row_stride(radeonContextPtr rmesa, mesa_format format
        } else {
                unsigned row_align;
 
-               if (!_mesa_is_pow_two(width) || target == GL_TEXTURE_RECTANGLE) {
+               if (!util_is_power_of_two_or_zero(width) || target == GL_TEXTURE_RECTANGLE) {
                        row_align = rmesa->texture_rect_row_align - 1;
                } else if (tiling) {
                        unsigned tileWidth, tileHeight;
@@ -129,7 +129,7 @@ static void compute_tex_image_offset(radeonContextPtr rmesa, radeon_mipmap_tree
        radeon_mipmap_level *lvl = &mt->levels[level];
        GLuint height;
 
-       height = _mesa_next_pow_two_32(lvl->height);
+       height = util_next_power_of_two(lvl->height);
 
        lvl->rowstride = get_texture_image_row_stride(rmesa, mt->mesaFormat, lvl->width, mt->tilebits, mt->target);
        lvl->size = get_texture_image_size(mt->mesaFormat, lvl->rowstride, height, lvl->depth, mt->tilebits);
@@ -150,7 +150,7 @@ static void calculate_miptree_layout(radeonContextPtr rmesa, radeon_mipmap_tree
 {
        GLuint curOffset, i, face, level;
 
-       assert(mt->numLevels <= rmesa->glCtx.Const.MaxTextureLevels);
+       assert(1 << (mt->numLevels - 1) <= rmesa->glCtx.Const.MaxTextureSize);
 
        curOffset = 0;
        for(face = 0; face < mt->faces; face++) {