Merge remote branch 'origin/master' into nvc0-new

[mesa.git] / src / mesa / drivers / dri / radeon / radeon_mipmap_tree.h

diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h
index a10649b5aeac8ee961d48b04c39f84bb62a44417..a68a97687799562b15d9dfcb0234544a7bc86bf1 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h
@@ -49,7 +49,7 @@ struct _radeon_mipmap_level {
 };
 
 /* store the max possible in the miptree */
-#define RADEON_MIPTREE_MAX_TEXTURE_LEVELS 13
+#define RADEON_MIPTREE_MAX_TEXTURE_LEVELS 15
 
 /**
  * A mipmap tree contains texture images in the layout that the hardware
@@ -88,7 +88,14 @@ GLboolean radeon_miptree_matches_image(radeon_mipmap_tree *mt,
 void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t);
 GLuint radeon_miptree_image_offset(radeon_mipmap_tree *mt,
                                   GLuint face, GLuint level);
-void radeon_miptree_depth_offsets(radeon_mipmap_tree *mt, GLuint level, GLuint *offsets);
-
 uint32_t get_base_teximage_offset(radeonTexObj *texObj);
+
+unsigned get_texture_image_row_stride(radeonContextPtr rmesa, gl_format format, unsigned width, unsigned tiling);
+
+unsigned get_texture_image_size(
+               gl_format format,
+               unsigned rowStride,
+               unsigned height,
+               unsigned depth,
+               unsigned tiling);
 #endif /* __RADEON_MIPMAP_TREE_H_ */