i965: Unify shader interfaces explicitly.
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_mipmap_tree.h
index a10649b5aeac8ee961d48b04c39f84bb62a44417..f919a581b520fdd48a978d53a8275aeefc1f4d4b 100644 (file)
@@ -49,7 +49,7 @@ struct _radeon_mipmap_level {
 };
 
 /* store the max possible in the miptree */
-#define RADEON_MIPTREE_MAX_TEXTURE_LEVELS 13
+#define RADEON_MIPTREE_MAX_TEXTURE_LEVELS 15
 
 /**
  * A mipmap tree contains texture images in the layout that the hardware
@@ -84,11 +84,23 @@ void radeon_miptree_reference(radeon_mipmap_tree *mt, radeon_mipmap_tree **ptr);
 void radeon_miptree_unreference(radeon_mipmap_tree **ptr);
 
 GLboolean radeon_miptree_matches_image(radeon_mipmap_tree *mt,
-               struct gl_texture_image *texImage, GLuint face, GLuint level);
+                                      struct gl_texture_image *texImage);
+                                      
 void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t);
 GLuint radeon_miptree_image_offset(radeon_mipmap_tree *mt,
                                   GLuint face, GLuint level);
-void radeon_miptree_depth_offsets(radeon_mipmap_tree *mt, GLuint level, GLuint *offsets);
-
 uint32_t get_base_teximage_offset(radeonTexObj *texObj);
+
+unsigned get_texture_image_row_stride(radeonContextPtr rmesa, mesa_format format, unsigned width, unsigned tiling, unsigned target);
+
+unsigned get_texture_image_size(
+               mesa_format format,
+               unsigned rowStride,
+               unsigned height,
+               unsigned depth,
+               unsigned tiling);
+
+radeon_mipmap_tree *radeon_miptree_create(radeonContextPtr rmesa,
+                                         GLenum target, mesa_format mesaFormat, GLuint baseLevel, GLuint numLevels,
+                                         GLuint width0, GLuint height0, GLuint depth0, GLuint tilebits);
 #endif /* __RADEON_MIPMAP_TREE_H_ */