i965/vec4: Combine generate_math[12]_gen6 methods.

[mesa.git] / src / mesa / drivers / dri / radeon / radeon_queryobj.c

diff --git a/src/mesa/drivers/dri/radeon/radeon_queryobj.c b/src/mesa/drivers/dri/radeon/radeon_queryobj.c
index a45ca7cad0d1ddb4332433bd4c46323a4ac8016e..7efe52f0ef0b73f4ba9a4834a689734d06d213c3 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_queryobj.c
+++ b/src/mesa/drivers/dri/radeon/radeon_queryobj.c
@@ -35,7 +35,6 @@
 
 static void radeonQueryGetResult(struct gl_context *ctx, struct gl_query_object *q)
 {
-       radeonContextPtr radeon = RADEON_CONTEXT(ctx);
        struct radeon_query_object *query = (struct radeon_query_object *)q;
         uint32_t *result;
        int i;
@@ -48,32 +47,9 @@ static void radeonQueryGetResult(struct gl_context *ctx, struct gl_query_object
         result = query->bo->ptr;
 
        query->Base.Result = 0;
-       if (IS_R600_CLASS(radeon->radeonScreen)) {
-               /* ZPASS EVENT writes alternating qwords
-                * At query start we set the start offset to 0 and
-                * hw writes zpass start counts to qwords 0, 2, 4, 6.
-                * At query end we set the start offset to 8 and
-                * hw writes zpass end counts to qwords 1, 3, 5, 7.
-                * then we substract. MSB is the valid bit.
-                */
-               for (i = 0; i < 32; i += 4) {
-                       uint64_t start = (uint64_t)LE32_TO_CPU(result[i]) |
-                                        (uint64_t)LE32_TO_CPU(result[i + 1]) << 32;
-                       uint64_t end = (uint64_t)LE32_TO_CPU(result[i + 2]) |
-                                      (uint64_t)LE32_TO_CPU(result[i + 3]) << 32;
-                       if ((start & 0x8000000000000000) && (end & 0x8000000000000000)) {
-                               uint64_t query_count = end - start;
-                               query->Base.Result += query_count;
-
-                       }
-                       radeon_print(RADEON_STATE, RADEON_TRACE,
-                                    "%d start: %" PRIu64 ", end: %" PRIu64 " %" PRIu64 "\n", i, start, end, end - start);
-               }
-       } else {
-               for (i = 0; i < query->curr_offset/sizeof(uint32_t); ++i) {
-                       query->Base.Result += LE32_TO_CPU(result[i]);
-                       radeon_print(RADEON_STATE, RADEON_TRACE, "result[%d] = %d\n", i, LE32_TO_CPU(result[i]));
-               }
+       for (i = 0; i < query->curr_offset/sizeof(uint32_t); ++i) {
+               query->Base.Result += LE32_TO_CPU(result[i]);
+               radeon_print(RADEON_STATE, RADEON_TRACE, "result[%d] = %d\n", i, LE32_TO_CPU(result[i]));
        }
 
        radeon_bo_unmap(query->bo);
@@ -135,7 +111,7 @@ static void radeonBeginQuery(struct gl_context *ctx, struct gl_query_object *q)
        assert(radeon->query.current == NULL);
 
        if (radeon->dma.flush)
-               radeon->dma.flush(radeon->glCtx);
+               radeon->dma.flush(&radeon->glCtx);
 
        if (!query->bo) {
                query->bo = radeon_bo_open(radeon->radeonScreen->bom, 0, RADEON_QUERY_PAGE_SIZE, RADEON_QUERY_PAGE_SIZE, RADEON_GEM_DOMAIN_GTT, 0);
@@ -175,7 +151,7 @@ static void radeonEndQuery(struct gl_context *ctx, struct gl_query_object *q)
        radeon_print(RADEON_STATE, RADEON_NORMAL, "%s: query id %d\n", __FUNCTION__, q->Id);
 
        if (radeon->dma.flush)
-               radeon->dma.flush(radeon->glCtx);
+               radeon->dma.flush(&radeon->glCtx);
        radeonEmitQueryEnd(ctx);
 
        radeon->query.current = NULL;
@@ -184,25 +160,21 @@ static void radeonEndQuery(struct gl_context *ctx, struct gl_query_object *q)
 static void radeonCheckQuery(struct gl_context *ctx, struct gl_query_object *q)
 {
        radeon_print(RADEON_STATE, RADEON_TRACE, "%s: query id %d\n", __FUNCTION__, q->Id);
-
+\
 #ifdef DRM_RADEON_GEM_BUSY
        radeonContextPtr radeon = RADEON_CONTEXT(ctx);
 
-       if (radeon->radeonScreen->kernel_mm) {
-               struct radeon_query_object *query = (struct radeon_query_object *)q;
-               uint32_t domain;
-
-               /* Need to perform a flush, as per ARB_occlusion_query spec */
-               if (radeon_bo_is_referenced_by_cs(query->bo, radeon->cmdbuf.cs)) {
-                       ctx->Driver.Flush(ctx);
-               }
-
-               if (radeon_bo_is_busy(query->bo, &domain) == 0) {
-                       radeonQueryGetResult(ctx, q);
-                       query->Base.Ready = GL_TRUE;
-               }
-       } else {
-               radeonWaitQuery(ctx, q);
+       struct radeon_query_object *query = (struct radeon_query_object *)q;
+       uint32_t domain;
+
+       /* Need to perform a flush, as per ARB_occlusion_query spec */
+       if (radeon_bo_is_referenced_by_cs(query->bo, radeon->cmdbuf.cs)) {
+               ctx->Driver.Flush(ctx);
+       }
+
+       if (radeon_bo_is_busy(query->bo, &domain) == 0) {
+               radeonQueryGetResult(ctx, q);
+               query->Base.Ready = GL_TRUE;
        }
 #else
        radeonWaitQuery(ctx, q);
@@ -237,7 +209,7 @@ void radeon_emit_queryobj(struct gl_context *ctx, struct radeon_state_atom *atom
 
        dwords = (*atom->check) (ctx, atom);
 
-       BEGIN_BATCH_NO_AUTOSTATE(dwords);
+       BEGIN_BATCH(dwords);
        OUT_BATCH_TABLE(atom->cmd, dwords);
        END_BATCH();