Refactor "class" texture environments to be implemented in terms of

[mesa.git] / src / mesa / drivers / dri / radeon / radeon_sanity.c

diff --git a/src/mesa/drivers/dri/radeon/radeon_sanity.c b/src/mesa/drivers/dri/radeon/radeon_sanity.c
index e3b37bf3de9124157d1f76fe3ac03464e80d360f..451c73cf25e8a98731eaeadaacd6ae370f9a429a 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_sanity.c
+++ b/src/mesa/drivers/dri/radeon/radeon_sanity.c
@@ -1,4 +1,4 @@
-/* $XFree86$ */
+/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_sanity.c,v 1.1 2002/10/30 12:51:55 alanh Exp $ */
 /**************************************************************************
 
 Copyright 2002 ATI Technologies Inc., Ontario, Canada, and
@@ -32,7 +32,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
  *   Keith Whitwell <keith@tungstengraphics.com>
  *
  */
-#include <errno.h>
+#include <errno.h> 
 
 #include "glheader.h"
 
@@ -137,7 +137,7 @@ static struct {
        { 0, 5, "R200_PP_CUBIC_OFFSET_F1_5" },
    { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" },
    { RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" },
-   { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_1" },
+   { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" },
 };
 
 struct reg_names {
@@ -178,22 +178,22 @@ static struct reg_names reg_names[] = {
    { RADEON_PP_TXFILTER_2, "RADEON_PP_TXFILTER_2" },
    { RADEON_PP_TXFORMAT_0, "RADEON_PP_TXFORMAT_0" },
    { RADEON_PP_TXFORMAT_1, "RADEON_PP_TXFORMAT_1" },
-   { RADEON_PP_TXFORMAT_2, "RADEON_PP_TXFORMAT_3" },
+   { RADEON_PP_TXFORMAT_2, "RADEON_PP_TXFORMAT_2" },
    { RADEON_PP_TXOFFSET_0, "RADEON_PP_TXOFFSET_0" },
    { RADEON_PP_TXOFFSET_1, "RADEON_PP_TXOFFSET_1" },
-   { RADEON_PP_TXOFFSET_2, "RADEON_PP_TXOFFSET_3" },
+   { RADEON_PP_TXOFFSET_2, "RADEON_PP_TXOFFSET_2" },
    { RADEON_PP_TXCBLEND_0, "RADEON_PP_TXCBLEND_0" },
    { RADEON_PP_TXCBLEND_1, "RADEON_PP_TXCBLEND_1" },
-   { RADEON_PP_TXCBLEND_2, "RADEON_PP_TXCBLEND_3" },
+   { RADEON_PP_TXCBLEND_2, "RADEON_PP_TXCBLEND_2" },
    { RADEON_PP_TXABLEND_0, "RADEON_PP_TXABLEND_0" },
    { RADEON_PP_TXABLEND_1, "RADEON_PP_TXABLEND_1" },
-   { RADEON_PP_TXABLEND_2, "RADEON_PP_TXABLEND_3" },
+   { RADEON_PP_TXABLEND_2, "RADEON_PP_TXABLEND_2" },
    { RADEON_PP_TFACTOR_0, "RADEON_PP_TFACTOR_0" },
    { RADEON_PP_TFACTOR_1, "RADEON_PP_TFACTOR_1" },
-   { RADEON_PP_TFACTOR_2, "RADEON_PP_TFACTOR_3" },
+   { RADEON_PP_TFACTOR_2, "RADEON_PP_TFACTOR_2" },
    { RADEON_PP_BORDER_COLOR_0, "RADEON_PP_BORDER_COLOR_0" },
    { RADEON_PP_BORDER_COLOR_1, "RADEON_PP_BORDER_COLOR_1" },
-   { RADEON_PP_BORDER_COLOR_2, "RADEON_PP_BORDER_COLOR_3" },
+   { RADEON_PP_BORDER_COLOR_2, "RADEON_PP_BORDER_COLOR_2" },
    { RADEON_SE_ZBIAS_FACTOR, "RADEON_SE_ZBIAS_FACTOR" },
    { RADEON_SE_ZBIAS_CONSTANT, "RADEON_SE_ZBIAS_CONSTANT" },
    { RADEON_SE_TCL_OUTPUT_VTX_FMT, "RADEON_SE_TCL_OUTPUT_VTXFMT" },