Revert the move of lost_context setting to UNLOCK_HARDWARE that was done in the

[mesa.git] / src / mesa / drivers / dri / radeon / radeon_sanity.c

diff --git a/src/mesa/drivers/dri/radeon/radeon_sanity.c b/src/mesa/drivers/dri/radeon/radeon_sanity.c
index e3b37bf3de9124157d1f76fe3ac03464e80d360f..4a6d7d1b2a9d341cc5efc63d5827589ab4cb626b 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_sanity.c
+++ b/src/mesa/drivers/dri/radeon/radeon_sanity.c
@@ -1,4 +1,4 @@
-/* $XFree86$ */
+/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_sanity.c,v 1.1 2002/10/30 12:51:55 alanh Exp $ */
 /**************************************************************************
 
 Copyright 2002 ATI Technologies Inc., Ontario, Canada, and
@@ -32,7 +32,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
  *   Keith Whitwell <keith@tungstengraphics.com>
  *
  */
-#include <errno.h>
+#include <errno.h> 
 
 #include "glheader.h"
 
@@ -137,7 +137,8 @@ static struct {
        { 0, 5, "R200_PP_CUBIC_OFFSET_F1_5" },
    { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" },
    { RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" },
-   { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_1" },
+   { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" },
+       { 0, 3, "R200_RB3D_BLENDCOLOR" },
 };
 
 struct reg_names {
@@ -178,22 +179,22 @@ static struct reg_names reg_names[] = {
    { RADEON_PP_TXFILTER_2, "RADEON_PP_TXFILTER_2" },
    { RADEON_PP_TXFORMAT_0, "RADEON_PP_TXFORMAT_0" },
    { RADEON_PP_TXFORMAT_1, "RADEON_PP_TXFORMAT_1" },
-   { RADEON_PP_TXFORMAT_2, "RADEON_PP_TXFORMAT_3" },
+   { RADEON_PP_TXFORMAT_2, "RADEON_PP_TXFORMAT_2" },
    { RADEON_PP_TXOFFSET_0, "RADEON_PP_TXOFFSET_0" },
    { RADEON_PP_TXOFFSET_1, "RADEON_PP_TXOFFSET_1" },
-   { RADEON_PP_TXOFFSET_2, "RADEON_PP_TXOFFSET_3" },
+   { RADEON_PP_TXOFFSET_2, "RADEON_PP_TXOFFSET_2" },
    { RADEON_PP_TXCBLEND_0, "RADEON_PP_TXCBLEND_0" },
    { RADEON_PP_TXCBLEND_1, "RADEON_PP_TXCBLEND_1" },
-   { RADEON_PP_TXCBLEND_2, "RADEON_PP_TXCBLEND_3" },
+   { RADEON_PP_TXCBLEND_2, "RADEON_PP_TXCBLEND_2" },
    { RADEON_PP_TXABLEND_0, "RADEON_PP_TXABLEND_0" },
    { RADEON_PP_TXABLEND_1, "RADEON_PP_TXABLEND_1" },
-   { RADEON_PP_TXABLEND_2, "RADEON_PP_TXABLEND_3" },
+   { RADEON_PP_TXABLEND_2, "RADEON_PP_TXABLEND_2" },
    { RADEON_PP_TFACTOR_0, "RADEON_PP_TFACTOR_0" },
    { RADEON_PP_TFACTOR_1, "RADEON_PP_TFACTOR_1" },
-   { RADEON_PP_TFACTOR_2, "RADEON_PP_TFACTOR_3" },
+   { RADEON_PP_TFACTOR_2, "RADEON_PP_TFACTOR_2" },
    { RADEON_PP_BORDER_COLOR_0, "RADEON_PP_BORDER_COLOR_0" },
    { RADEON_PP_BORDER_COLOR_1, "RADEON_PP_BORDER_COLOR_1" },
-   { RADEON_PP_BORDER_COLOR_2, "RADEON_PP_BORDER_COLOR_3" },
+   { RADEON_PP_BORDER_COLOR_2, "RADEON_PP_BORDER_COLOR_2" },
    { RADEON_SE_ZBIAS_FACTOR, "RADEON_SE_ZBIAS_FACTOR" },
    { RADEON_SE_ZBIAS_CONSTANT, "RADEON_SE_ZBIAS_CONSTANT" },
    { RADEON_SE_TCL_OUTPUT_VTX_FMT, "RADEON_SE_TCL_OUTPUT_VTXFMT" },
@@ -487,8 +488,8 @@ static void dump_state( void )
 
 
 static int radeon_emit_packets( 
-   drmRadeonCmdHeader header,
-   drmRadeonCmdBuffer *cmdbuf )
+   drm_radeon_cmd_header_t header,
+   drm_radeon_cmd_buffer_t *cmdbuf )
 {
    int id = (int)header.packet.packet_id;
    int sz = packet[id].len;
@@ -523,8 +524,8 @@ static int radeon_emit_packets(
 
 
 static int radeon_emit_scalars( 
-   drmRadeonCmdHeader header,
-   drmRadeonCmdBuffer *cmdbuf )
+   drm_radeon_cmd_header_t header,
+   drm_radeon_cmd_buffer_t *cmdbuf )
 {
    int sz = header.scalars.count;
    int *data = (int *)cmdbuf->buf;
@@ -551,8 +552,8 @@ static int radeon_emit_scalars(
 
 
 static int radeon_emit_scalars2( 
-   drmRadeonCmdHeader header,
-   drmRadeonCmdBuffer *cmdbuf )
+   drm_radeon_cmd_header_t header,
+   drm_radeon_cmd_buffer_t *cmdbuf )
 {
    int sz = header.scalars.count;
    int *data = (int *)cmdbuf->buf;
@@ -585,8 +586,8 @@ static int radeon_emit_scalars2(
  * Check: table start, end, nr, etc.
  */
 static int radeon_emit_vectors( 
-   drmRadeonCmdHeader header,
-   drmRadeonCmdBuffer *cmdbuf )
+   drm_radeon_cmd_header_t header,
+   drm_radeon_cmd_buffer_t *cmdbuf )
 {
    int sz = header.vectors.count;
    int *data = (int *)cmdbuf->buf;
@@ -746,7 +747,7 @@ static int print_prim_and_flags( int prim )
 
 /* build in knowledge about each packet type
  */
-static int radeon_emit_packet3( drmRadeonCmdBuffer *cmdbuf )
+static int radeon_emit_packet3( drm_radeon_cmd_buffer_t *cmdbuf )
 {
    int cmdsz;
    int *cmd = (int *)cmdbuf->buf;
@@ -907,9 +908,9 @@ static int radeon_emit_packet3( drmRadeonCmdBuffer *cmdbuf )
 
 /* Check cliprects for bounds, then pass on to above:
  */
-static int radeon_emit_packet3_cliprect( drmRadeonCmdBuffer *cmdbuf )
+static int radeon_emit_packet3_cliprect( drm_radeon_cmd_buffer_t *cmdbuf )
 {   
-   XF86DRIClipRectRec *boxes = (XF86DRIClipRectRec *)cmdbuf->boxes;
+   drm_clip_rect_t *boxes = cmdbuf->boxes;
    int i = 0;
 
    if (VERBOSE && total_changed) {
@@ -937,11 +938,11 @@ static int radeon_emit_packet3_cliprect( drmRadeonCmdBuffer *cmdbuf )
 
 int radeonSanityCmdBuffer( radeonContextPtr rmesa,
                           int nbox,
-                          XF86DRIClipRectRec *boxes )
+                          drm_clip_rect_t *boxes )
 {
    int idx;
-   drmRadeonCmdBuffer cmdbuf;
-   drmRadeonCmdHeader header;
+   drm_radeon_cmd_buffer_t cmdbuf;
+   drm_radeon_cmd_header_t header;
    static int inited = 0;
 
    if (!inited) {
@@ -951,7 +952,7 @@ int radeonSanityCmdBuffer( radeonContextPtr rmesa,
 
    cmdbuf.buf = rmesa->store.cmd_buf;
    cmdbuf.bufsz = rmesa->store.cmd_used;
-   cmdbuf.boxes = (drmClipRect *)boxes;
+   cmdbuf.boxes = boxes;
    cmdbuf.nbox = nbox;
 
    while ( cmdbuf.bufsz >= sizeof(header) ) {