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Merge remote branch 'main/radeon-rewrite'
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_sanity.c
diff --git a/src/mesa/drivers/dri/radeon/radeon_sanity.c b/src/mesa/drivers/dri/radeon/radeon_sanity.c
index 451c73cf25e8a98731eaeadaacd6ae370f9a429a..bbed838b592dcff737e2182f495cf171ff144a31 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_sanity.c
+++ b/src/mesa/drivers/dri/radeon/radeon_sanity.c
@@ -1,4 +1,3 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_sanity.c,v 1.1 2002/10/30 12:51:55 alanh Exp $ */
 /**************************************************************************
 
 Copyright 2002 ATI Technologies Inc., Ontario, Canada, and
@@ -34,7 +33,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
  */
 #include <errno.h> 
 
-#include "glheader.h"
+#include "main/glheader.h"
 
 #include "radeon_context.h"
 #include "radeon_ioctl.h"
@@ -138,6 +137,25 @@ static struct {
    { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" },
    { RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" },
    { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" },
+       { 0, 3, "R200_RB3D_BLENDCOLOR" },
+       { 0, 1, "R200_SE_TCL_POINT_SPRITE_CNTL" },
+   { RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0" },
+   { RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0" },
+   { RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1" },
+   { RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0" },
+   { RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2" },
+   { RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0" },
+   { 0, 2, "R200_PP_TRI_PERF" },
+   { 0, 32, "R200_PP_AFS_0"},   /* 85 */
+   { 0, 32, "R200_PP_AFS_1"},
+   { 0, 8, "R200_ATF_TFACTOR"},
+   { 0, 8, "R200_PP_TXCTLALL_0"},
+   { 0, 8, "R200_PP_TXCTLALL_1"},
+   { 0, 8, "R200_PP_TXCTLALL_2"},
+   { 0, 8, "R200_PP_TXCTLALL_3"},
+   { 0, 8, "R200_PP_TXCTLALL_4"},
+   { 0, 8, "R200_PP_TXCTLALL_5"},
+   { 0, 2, "R200_VAP_PVS_CNTL"},
 };
 
 struct reg_names {
@@ -231,6 +249,24 @@ static struct reg_names reg_names[] = {
    { RADEON_PP_TEX_SIZE_0+4, "RADEON_PP_TEX_PITCH_0" },
    { RADEON_PP_TEX_SIZE_1+4, "RADEON_PP_TEX_PITCH_1" },
    { RADEON_PP_TEX_SIZE_2+4, "RADEON_PP_TEX_PITCH_2" },
+   { RADEON_PP_CUBIC_FACES_0, "RADEON_PP_CUBIC_FACES_0" },
+   { RADEON_PP_CUBIC_FACES_1, "RADEON_PP_CUBIC_FACES_1" },
+   { RADEON_PP_CUBIC_FACES_2, "RADEON_PP_CUBIC_FACES_2" },
+   { RADEON_PP_CUBIC_OFFSET_T0_0, "RADEON_PP_CUBIC_OFFSET_T0_0" },
+   { RADEON_PP_CUBIC_OFFSET_T0_1, "RADEON_PP_CUBIC_OFFSET_T0_1" },
+   { RADEON_PP_CUBIC_OFFSET_T0_2, "RADEON_PP_CUBIC_OFFSET_T0_2" },
+   { RADEON_PP_CUBIC_OFFSET_T0_3, "RADEON_PP_CUBIC_OFFSET_T0_3" },
+   { RADEON_PP_CUBIC_OFFSET_T0_4, "RADEON_PP_CUBIC_OFFSET_T0_4" },
+   { RADEON_PP_CUBIC_OFFSET_T1_0, "RADEON_PP_CUBIC_OFFSET_T1_0" },
+   { RADEON_PP_CUBIC_OFFSET_T1_1, "RADEON_PP_CUBIC_OFFSET_T1_1" },
+   { RADEON_PP_CUBIC_OFFSET_T1_2, "RADEON_PP_CUBIC_OFFSET_T1_2" },
+   { RADEON_PP_CUBIC_OFFSET_T1_3, "RADEON_PP_CUBIC_OFFSET_T1_3" },
+   { RADEON_PP_CUBIC_OFFSET_T1_4, "RADEON_PP_CUBIC_OFFSET_T1_4" },
+   { RADEON_PP_CUBIC_OFFSET_T2_0, "RADEON_PP_CUBIC_OFFSET_T2_0" },
+   { RADEON_PP_CUBIC_OFFSET_T2_1, "RADEON_PP_CUBIC_OFFSET_T2_1" },
+   { RADEON_PP_CUBIC_OFFSET_T2_2, "RADEON_PP_CUBIC_OFFSET_T2_2" },
+   { RADEON_PP_CUBIC_OFFSET_T2_3, "RADEON_PP_CUBIC_OFFSET_T2_3" },
+   { RADEON_PP_CUBIC_OFFSET_T2_4, "RADEON_PP_CUBIC_OFFSET_T2_4" },
 };
 
 static struct reg_names scalar_names[] = {
@@ -309,7 +345,7 @@ static void init_regs( void )
    struct reg_names *tmp;
    int i;
 
-   for (i = 0 ; i < Elements(regs) ; i++) {
+   for (i = 0 ; i < Elements(regs)-1 ; i++) {
       regs[i].idx = reg_names[i].idx;
       regs[i].closest = &reg_names[i];
       regs[i].flags = 0;
@@ -363,7 +399,7 @@ static struct reg *lookup_reg( struct reg *tab, int reg )
    }
 
    fprintf(stderr, "*** unknown reg 0x%x\n", reg);
-   return 0;
+   return NULL;
 }
 
 
@@ -451,9 +487,11 @@ static int print_float_reg_assignment( struct reg *reg, float data )
 
 static int print_reg_assignment( struct reg *reg, int data )
 {
+   float_ui32_type datau;
+   datau.ui32 = data;
    reg->flags |= TOUCHED;
    if (reg->flags & ISFLOAT)
-      return print_float_reg_assignment( reg, *(float *)&data );
+      return print_float_reg_assignment( reg, datau.f );
    else
       return print_int_reg_assignment( reg, data );
 }
@@ -487,8 +525,8 @@ static void dump_state( void )
 
 
 static int radeon_emit_packets( 
-   drmRadeonCmdHeader header,
-   drmRadeonCmdBuffer *cmdbuf )
+   drm_radeon_cmd_header_t header,
+   drm_radeon_cmd_buffer_t *cmdbuf )
 {
    int id = (int)header.packet.packet_id;
    int sz = packet[id].len;
@@ -523,8 +561,8 @@ static int radeon_emit_packets(
 
 
 static int radeon_emit_scalars( 
-   drmRadeonCmdHeader header,
-   drmRadeonCmdBuffer *cmdbuf )
+   drm_radeon_cmd_header_t header,
+   drm_radeon_cmd_buffer_t *cmdbuf )
 {
    int sz = header.scalars.count;
    int *data = (int *)cmdbuf->buf;
@@ -551,8 +589,8 @@ static int radeon_emit_scalars(
 
 
 static int radeon_emit_scalars2( 
-   drmRadeonCmdHeader header,
-   drmRadeonCmdBuffer *cmdbuf )
+   drm_radeon_cmd_header_t header,
+   drm_radeon_cmd_buffer_t *cmdbuf )
 {
    int sz = header.scalars.count;
    int *data = (int *)cmdbuf->buf;
@@ -585,8 +623,8 @@ static int radeon_emit_scalars2(
  * Check: table start, end, nr, etc.
  */
 static int radeon_emit_vectors( 
-   drmRadeonCmdHeader header,
-   drmRadeonCmdBuffer *cmdbuf )
+   drm_radeon_cmd_header_t header,
+   drm_radeon_cmd_buffer_t *cmdbuf )
 {
    int sz = header.vectors.count;
    int *data = (int *)cmdbuf->buf;
@@ -746,7 +784,7 @@ static int print_prim_and_flags( int prim )
 
 /* build in knowledge about each packet type
  */
-static int radeon_emit_packet3( drmRadeonCmdBuffer *cmdbuf )
+static int radeon_emit_packet3( drm_radeon_cmd_buffer_t *cmdbuf )
 {
    int cmdsz;
    int *cmd = (int *)cmdbuf->buf;
@@ -907,9 +945,9 @@ static int radeon_emit_packet3( drmRadeonCmdBuffer *cmdbuf )
 
 /* Check cliprects for bounds, then pass on to above:
  */
-static int radeon_emit_packet3_cliprect( drmRadeonCmdBuffer *cmdbuf )
+static int radeon_emit_packet3_cliprect( drm_radeon_cmd_buffer_t *cmdbuf )
 {   
-   XF86DRIClipRectRec *boxes = (XF86DRIClipRectRec *)cmdbuf->boxes;
+   drm_clip_rect_t *boxes = cmdbuf->boxes;
    int i = 0;
 
    if (VERBOSE && total_changed) {
@@ -935,13 +973,13 @@ static int radeon_emit_packet3_cliprect( drmRadeonCmdBuffer *cmdbuf )
 }
 
 
-int radeonSanityCmdBuffer( radeonContextPtr rmesa,
+int radeonSanityCmdBuffer( r100ContextPtr rmesa,
                           int nbox,
-                          XF86DRIClipRectRec *boxes )
+                          drm_clip_rect_t *boxes )
 {
    int idx;
-   drmRadeonCmdBuffer cmdbuf;
-   drmRadeonCmdHeader header;
+   drm_radeon_cmd_buffer_t cmdbuf;
+   drm_radeon_cmd_header_t header;
    static int inited = 0;
 
    if (!inited) {
@@ -951,7 +989,7 @@ int radeonSanityCmdBuffer( radeonContextPtr rmesa,
 
    cmdbuf.buf = rmesa->store.cmd_buf;
    cmdbuf.bufsz = rmesa->store.cmd_used;
-   cmdbuf.boxes = (drmClipRect *)boxes;
+   cmdbuf.boxes = boxes;
    cmdbuf.nbox = nbox;
 
    while ( cmdbuf.bufsz >= sizeof(header) ) {