#include "swrast/s_renderbuffer.h"
#include "radeon_chipset.h"
-#include "radeon_macros.h"
#include "radeon_screen.h"
#include "radeon_common.h"
#include "radeon_common_context.h"
/* Radeon configuration
*/
-#include "xmlpool.h"
+#include "util/xmlpool.h"
#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
DRI_CONF_OPT_END
+#define DRI_CONF_MAX_TEXTURE_UNITS(def,min,max) \
+DRI_CONF_OPT_BEGIN_V(texture_units,int,def, # min ":" # max ) \
+ DRI_CONF_DESC(en,"Number of texture units used") \
+DRI_CONF_OPT_END
+
+#define DRI_CONF_HYPERZ(def) \
+DRI_CONF_OPT_BEGIN_B(hyperz, def) \
+ DRI_CONF_DESC(en,"Use HyperZ to boost performance") \
+DRI_CONF_OPT_END
+
#if defined(RADEON_R100) /* R100 */
static const __DRIconfigOptionsExtension radeon_config_options = {
.base = { __DRI_CONFIG_OPTIONS, 1 },
DRI_CONF_SECTION_PERFORMANCE
DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
- DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
DRI_CONF_HYPERZ("false")
DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
DRI_CONF_NO_NEG_LOD_BIAS("false")
- DRI_CONF_FORCE_S3TC_ENABLE("false")
DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
DRI_CONF_SECTION_END
- DRI_CONF_SECTION_DEBUG
- DRI_CONF_NO_RAST("false")
- DRI_CONF_SECTION_END
DRI_CONF_END
};
#elif defined(RADEON_R200)
+
+#define DRI_CONF_TEXTURE_BLEND_QUALITY(def,range) \
+DRI_CONF_OPT_BEGIN_V(texture_blend_quality,float,def,range) \
+ DRI_CONF_DESC(en,"Texture filtering quality vs. speed, AKA “brilinear” texture filtering") \
+DRI_CONF_OPT_END
+
static const __DRIconfigOptionsExtension radeon_config_options = {
.base = { __DRI_CONFIG_OPTIONS, 1 },
.xml =
DRI_CONF_SECTION_PERFORMANCE
DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
- DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
DRI_CONF_HYPERZ("false")
DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
DRI_CONF_NO_NEG_LOD_BIAS("false")
- DRI_CONF_FORCE_S3TC_ENABLE("false")
DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
DRI_CONF_SECTION_END
- DRI_CONF_SECTION_DEBUG
- DRI_CONF_NO_RAST("false")
- DRI_CONF_SECTION_END
DRI_CONF_END
};
#endif
-#ifndef RADEON_INFO_TILE_CONFIG
-#define RADEON_INFO_TILE_CONFIG 0x6
-#endif
-
static int
radeonGetParam(__DRIscreen *sPriv, int param, void *value)
{
- int ret;
- drm_radeon_getparam_t gp = { 0 };
struct drm_radeon_info info = { 0 };
- if (sPriv->drm_version.major >= 2) {
- info.value = (uint64_t)(uintptr_t)value;
- switch (param) {
- case RADEON_PARAM_DEVICE_ID:
- info.request = RADEON_INFO_DEVICE_ID;
- break;
- case RADEON_PARAM_NUM_GB_PIPES:
- info.request = RADEON_INFO_NUM_GB_PIPES;
- break;
- case RADEON_PARAM_NUM_Z_PIPES:
- info.request = RADEON_INFO_NUM_Z_PIPES;
- break;
- case RADEON_INFO_TILE_CONFIG:
- info.request = RADEON_INFO_TILE_CONFIG;
- break;
- default:
- return -EINVAL;
- }
- ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_INFO, &info, sizeof(info));
- } else {
- gp.param = param;
- gp.value = value;
-
- ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp));
+ info.value = (uint64_t)(uintptr_t)value;
+ switch (param) {
+ case RADEON_PARAM_DEVICE_ID:
+ info.request = RADEON_INFO_DEVICE_ID;
+ break;
+ case RADEON_PARAM_NUM_GB_PIPES:
+ info.request = RADEON_INFO_NUM_GB_PIPES;
+ break;
+ case RADEON_PARAM_NUM_Z_PIPES:
+ info.request = RADEON_INFO_NUM_Z_PIPES;
+ break;
+ case RADEON_INFO_TILING_CONFIG:
+ info.request = RADEON_INFO_TILING_CONFIG;
+ break;
+ default:
+ return -EINVAL;
}
- return ret;
+ return drmCommandWriteRead(sPriv->fd, DRM_RADEON_INFO, &info, sizeof(info));
}
#if defined(RADEON_R100)
static const __DRItexBufferExtension radeonTexBufferExtension = {
- { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
- radeonSetTexBuffer,
- radeonSetTexBuffer2,
+ .base = { __DRI_TEX_BUFFER, 3 },
+
+ .setTexBuffer = radeonSetTexBuffer,
+ .setTexBuffer2 = radeonSetTexBuffer2,
+ .releaseTexBuffer = NULL,
};
#elif defined(RADEON_R200)
static const __DRItexBufferExtension r200TexBufferExtension = {
- { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
- r200SetTexBuffer,
- r200SetTexBuffer2,
+ .base = { __DRI_TEX_BUFFER, 3 },
+
+ .setTexBuffer = r200SetTexBuffer,
+ .setTexBuffer2 = r200SetTexBuffer2,
+ .releaseTexBuffer = NULL,
};
#endif
}
}
-static struct __DRIimageExtensionRec radeonImageExtension = {
- { __DRI_IMAGE, 1 },
- radeon_create_image_from_name,
- radeon_create_image_from_renderbuffer,
- radeon_destroy_image,
- radeon_create_image,
- radeon_query_image
+static const __DRIimageExtension radeonImageExtension = {
+ .base = { __DRI_IMAGE, 1 },
+
+ .createImageFromName = radeon_create_image_from_name,
+ .createImageFromRenderbuffer = radeon_create_image_from_renderbuffer,
+ .destroyImage = radeon_destroy_image,
+ .createImage = radeon_create_image,
+ .queryImage = radeon_query_image
};
static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id)
return 0;
}
+static int
+radeonQueryRendererInteger(__DRIscreen *psp, int param,
+ unsigned int *value)
+{
+ radeonScreenPtr screen = (radeonScreenPtr)psp->driverPrivate;
+
+ switch (param) {
+ case __DRI2_RENDERER_VENDOR_ID:
+ value[0] = 0x1002;
+ return 0;
+ case __DRI2_RENDERER_DEVICE_ID:
+ value[0] = screen->device_id;
+ return 0;
+ case __DRI2_RENDERER_ACCELERATED:
+ value[0] = 1;
+ return 0;
+ case __DRI2_RENDERER_VIDEO_MEMORY: {
+ struct drm_radeon_gem_info gem_info;
+ int retval;
+ memset(&gem_info, 0, sizeof(gem_info));
+
+ /* Get GEM info. */
+ retval = drmCommandWriteRead(psp->fd, DRM_RADEON_GEM_INFO, &gem_info,
+ sizeof(gem_info));
+
+ if (retval) {
+ fprintf(stderr, "radeon: Failed to get MM info, error number %d\n",
+ retval);
+ return -1;
+
+ }
+ /* XXX: Do we want to return vram_size or vram_visible ? */
+ value[0] = gem_info.vram_size >> 20;
+ return 0;
+ }
+ case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE:
+ value[0] = 0;
+ return 0;
+ default:
+ return driQueryRendererIntegerCommon(psp, param, value);
+ }
+}
+
+static int
+radeonQueryRendererString(__DRIscreen *psp, int param, const char **value)
+{
+ radeonScreenPtr screen = (radeonScreenPtr)psp->driverPrivate;
+
+ switch (param) {
+ case __DRI2_RENDERER_VENDOR_ID:
+ value[0] = radeonVendorString;
+ return 0;
+ case __DRI2_RENDERER_DEVICE_ID:
+ value[0] = radeonGetRendererString(screen);
+ return 0;
+ default:
+ return -1;
+ }
+}
+
+static const __DRI2rendererQueryExtension radeonRendererQueryExtension = {
+ .base = { __DRI2_RENDERER_QUERY, 1 },
+
+ .queryInteger = radeonQueryRendererInteger,
+ .queryString = radeonQueryRendererString
+};
+
+
+static const __DRIextension *radeon_screen_extensions[] = {
+ &dri2ConfigQueryExtension.base,
+#if defined(RADEON_R100)
+ &radeonTexBufferExtension.base,
+#elif defined(RADEON_R200)
+ &r200TexBufferExtension.base,
+#endif
+ &radeonFlushExtension.base,
+ &radeonImageExtension.base,
+ &radeonRendererQueryExtension.base,
+ &dri2NoErrorExtension.base,
+ NULL
+};
+
static radeonScreenPtr
radeonCreateScreen2(__DRIscreen *sPriv)
{
radeonScreenPtr screen;
- int i;
int ret;
uint32_t device_id = 0;
/* Allocate the private area */
screen = calloc(1, sizeof(*screen));
if ( !screen ) {
- fprintf(stderr, "%s: Could not allocate memory for screen structure", __FUNCTION__);
+ fprintf(stderr, "%s: Could not allocate memory for screen structure", __func__);
fprintf(stderr, "leaving here\n");
return NULL;
}
if (getenv("RADEON_NO_TCL"))
screen->chip_flags &= ~RADEON_CHIPSET_TCL;
- i = 0;
- screen->extensions[i++] = &dri2ConfigQueryExtension.base;
-
-#if defined(RADEON_R100)
- screen->extensions[i++] = &radeonTexBufferExtension.base;
-#elif defined(RADEON_R200)
- screen->extensions[i++] = &r200TexBufferExtension.base;
-#endif
-
- screen->extensions[i++] = &radeonFlushExtension.base;
- screen->extensions[i++] = &radeonImageExtension.base;
-
- screen->extensions[i++] = NULL;
- sPriv->extensions = screen->extensions;
+ sPriv->extensions = radeon_screen_extensions;
screen->driScreen = sPriv;
screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd);
/* front color renderbuffer */
rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
- _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base.Base);
+ _mesa_attach_and_own_rb(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base.Base);
rfb->color_rb[0]->has_surface = 1;
/* back color renderbuffer */
if (mesaVis->doubleBufferMode) {
rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
- _mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base.Base);
+ _mesa_attach_and_own_rb(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base.Base);
rfb->color_rb[1]->has_surface = 1;
}
if (mesaVis->stencilBits == 8) {
struct radeon_renderbuffer *depthStencilRb =
radeon_create_renderbuffer(MESA_FORMAT_Z24_UNORM_S8_UINT, driDrawPriv);
- _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depthStencilRb->base.Base);
- _mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &depthStencilRb->base.Base);
+ _mesa_attach_and_own_rb(&rfb->base, BUFFER_DEPTH, &depthStencilRb->base.Base);
+ _mesa_attach_and_reference_rb(&rfb->base, BUFFER_STENCIL, &depthStencilRb->base.Base);
depthStencilRb->has_surface = screen->depthHasSurface;
} else {
/* depth renderbuffer */
struct radeon_renderbuffer *depth =
radeon_create_renderbuffer(MESA_FORMAT_Z24_UNORM_X8_UINT, driDrawPriv);
- _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base.Base);
+ _mesa_attach_and_own_rb(&rfb->base, BUFFER_DEPTH, &depth->base.Base);
depth->has_surface = screen->depthHasSurface;
}
} else if (mesaVis->depthBits == 16) {
/* just 16-bit depth buffer, no hw stencil */
struct radeon_renderbuffer *depth =
radeon_create_renderbuffer(MESA_FORMAT_Z_UNORM16, driDrawPriv);
- _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base.Base);
+ _mesa_attach_and_own_rb(&rfb->base, BUFFER_DEPTH, &depth->base.Base);
depth->has_surface = screen->depthHasSurface;
}
MESA_FORMAT_B8G8R8X8_UNORM,
MESA_FORMAT_B8G8R8A8_UNORM
};
- /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't
- * support pageflipping at all.
- */
+
static const GLenum back_buffer_modes[] = {
- GLX_NONE, GLX_SWAP_UNDEFINED_OML, /*, GLX_SWAP_COPY_OML*/
+ __DRI_ATTRIB_SWAP_NONE, __DRI_ATTRIB_SWAP_UNDEFINED
};
uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1];
int color;
ARRAY_SIZE(back_buffer_modes),
msaa_samples_array,
ARRAY_SIZE(msaa_samples_array),
- GL_TRUE);
+ GL_TRUE, GL_FALSE, GL_FALSE);
configs = driConcatConfigs(configs, new_configs);
}
projects / mesa.git / blobdiff