case PCI_CHIP_RV380_3150:
case PCI_CHIP_RV380_3152:
case PCI_CHIP_RV380_3154:
+ case PCI_CHIP_RV380_3155:
case PCI_CHIP_RV380_3E50:
case PCI_CHIP_RV380_3E54:
screen->chip_family = CHIP_FAMILY_RV380;
case PCI_CHIP_RV770_9456:
case PCI_CHIP_RV770_945A:
case PCI_CHIP_RV770_945B:
+ case PCI_CHIP_RV770_945E:
case PCI_CHIP_RV790_9460:
case PCI_CHIP_RV790_9462:
case PCI_CHIP_RV770_946A:
case PCI_CHIP_RV730_9487:
case PCI_CHIP_RV730_9488:
case PCI_CHIP_RV730_9489:
+ case PCI_CHIP_RV730_948A:
case PCI_CHIP_RV730_948F:
case PCI_CHIP_RV730_9490:
case PCI_CHIP_RV730_9491:
case PCI_CHIP_RV710_9553:
case PCI_CHIP_RV710_9555:
case PCI_CHIP_RV710_9557:
+ case PCI_CHIP_RV710_955F:
screen->chip_family = CHIP_FAMILY_RV710;
screen->chip_flags = RADEON_CHIPSET_TCL;
break;
/* pipe overrides */
switch (dri_priv->deviceID) {
case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
+ case PCI_CHIP_R350_AH: /* 9800 SE only have 1 quadpipe */
case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */
case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */
screen->num_gb_pipes = 1;
screen->extensions[i++] = &r600texOffsetExtension.base;
#endif
+ screen->extensions[i++] = &dri2ConfigQueryExtension.base;
+
screen->extensions[i++] = NULL;
sPriv->extensions = screen->extensions;
/* pipe overrides */
switch (device_id) {
case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
+ case PCI_CHIP_R350_AH: /* 9800 SE only have 1 quadpipe */
case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */
case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */
screen->num_gb_pipes = 1;