};
static __DRIimage *
-radeon_create_image_from_name(__DRIcontext *context,
+radeon_create_image_from_name(__DRIscreen *screen,
int width, int height, int format,
int name, int pitch, void *loaderPrivate)
{
__DRIimage *image;
- radeonContextPtr radeon = context->driverPrivate;
+ radeonScreenPtr radeonScreen = screen->private;
if (name == 0)
return NULL;
image->pitch = pitch;
image->height = height;
- image->bo = radeon_bo_open(radeon->radeonScreen->bom,
+ image->bo = radeon_bo_open(radeonScreen->bom,
(uint32_t)name,
image->pitch * image->height * image->cpp,
0,
break;
case PCI_CHIP_R200_BB:
- case PCI_CHIP_R200_BC:
case PCI_CHIP_R200_QH:
case PCI_CHIP_R200_QL:
case PCI_CHIP_R200_QM:
case PCI_CHIP_CEDAR_68E8:
case PCI_CHIP_CEDAR_68E9:
case PCI_CHIP_CEDAR_68F1:
+ case PCI_CHIP_CEDAR_68F2:
case PCI_CHIP_CEDAR_68F8:
case PCI_CHIP_CEDAR_68F9:
case PCI_CHIP_CEDAR_68FE:
case PCI_CHIP_JUNIPER_68B0:
case PCI_CHIP_JUNIPER_68B8:
case PCI_CHIP_JUNIPER_68B9:
+ case PCI_CHIP_JUNIPER_68BA:
case PCI_CHIP_JUNIPER_68BE:
+ case PCI_CHIP_JUNIPER_68BF:
screen->chip_family = CHIP_FAMILY_JUNIPER;
screen->chip_flags = RADEON_CHIPSET_TCL;
break;
case PCI_CHIP_CYPRESS_688A:
case PCI_CHIP_CYPRESS_6898:
case PCI_CHIP_CYPRESS_6899:
+ case PCI_CHIP_CYPRESS_689B:
case PCI_CHIP_CYPRESS_689E:
screen->chip_family = CHIP_FAMILY_CYPRESS;
screen->chip_flags = RADEON_CHIPSET_TCL;
screen->chip_flags = RADEON_CHIPSET_TCL;
break;
+ case PCI_CHIP_PALM_9802:
+ case PCI_CHIP_PALM_9803:
+ case PCI_CHIP_PALM_9804:
+ case PCI_CHIP_PALM_9805:
+ case PCI_CHIP_PALM_9806:
+ case PCI_CHIP_PALM_9807:
+ screen->chip_family = CHIP_FAMILY_PALM;
+ screen->chip_flags = RADEON_CHIPSET_TCL;
+ break;
+
+ case PCI_CHIP_SUMO_9640:
+ case PCI_CHIP_SUMO_9641:
+ case PCI_CHIP_SUMO_9647:
+ case PCI_CHIP_SUMO_9648:
+ case PCI_CHIP_SUMO_964A:
+ case PCI_CHIP_SUMO_964E:
+ case PCI_CHIP_SUMO_964F:
+ screen->chip_family = CHIP_FAMILY_SUMO;
+ screen->chip_flags = RADEON_CHIPSET_TCL;
+ break;
+
+ case PCI_CHIP_SUMO2_9642:
+ case PCI_CHIP_SUMO2_9643:
+ case PCI_CHIP_SUMO2_9644:
+ case PCI_CHIP_SUMO2_9645:
+ screen->chip_family = CHIP_FAMILY_SUMO2;
+ screen->chip_flags = RADEON_CHIPSET_TCL;
+ break;
+
+ case PCI_CHIP_BARTS_6720:
+ case PCI_CHIP_BARTS_6721:
+ case PCI_CHIP_BARTS_6722:
+ case PCI_CHIP_BARTS_6723:
+ case PCI_CHIP_BARTS_6724:
+ case PCI_CHIP_BARTS_6725:
+ case PCI_CHIP_BARTS_6726:
+ case PCI_CHIP_BARTS_6727:
+ case PCI_CHIP_BARTS_6728:
+ case PCI_CHIP_BARTS_6729:
+ case PCI_CHIP_BARTS_6738:
+ case PCI_CHIP_BARTS_6739:
+ case PCI_CHIP_BARTS_673E:
+ screen->chip_family = CHIP_FAMILY_BARTS;
+ screen->chip_flags = RADEON_CHIPSET_TCL;
+ break;
+
+ case PCI_CHIP_TURKS_6740:
+ case PCI_CHIP_TURKS_6741:
+ case PCI_CHIP_TURKS_6742:
+ case PCI_CHIP_TURKS_6743:
+ case PCI_CHIP_TURKS_6744:
+ case PCI_CHIP_TURKS_6745:
+ case PCI_CHIP_TURKS_6746:
+ case PCI_CHIP_TURKS_6747:
+ case PCI_CHIP_TURKS_6748:
+ case PCI_CHIP_TURKS_6749:
+ case PCI_CHIP_TURKS_6750:
+ case PCI_CHIP_TURKS_6758:
+ case PCI_CHIP_TURKS_6759:
+ case PCI_CHIP_TURKS_675F:
+ screen->chip_family = CHIP_FAMILY_TURKS;
+ screen->chip_flags = RADEON_CHIPSET_TCL;
+ break;
+
+ case PCI_CHIP_CAICOS_6760:
+ case PCI_CHIP_CAICOS_6761:
+ case PCI_CHIP_CAICOS_6762:
+ case PCI_CHIP_CAICOS_6763:
+ case PCI_CHIP_CAICOS_6764:
+ case PCI_CHIP_CAICOS_6765:
+ case PCI_CHIP_CAICOS_6766:
+ case PCI_CHIP_CAICOS_6767:
+ case PCI_CHIP_CAICOS_6768:
+ case PCI_CHIP_CAICOS_6770:
+ case PCI_CHIP_CAICOS_6778:
+ case PCI_CHIP_CAICOS_6779:
+ screen->chip_family = CHIP_FAMILY_CAICOS;
+ screen->chip_flags = RADEON_CHIPSET_TCL;
+ break;
+
default:
fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
device_id);
screen->chip_flags |= RADEON_CLASS_R600;
/* set group bytes for r6xx+ */
- screen->group_bytes = 256;
+ if (screen->chip_family >= CHIP_FAMILY_CEDAR)
+ screen->group_bytes = 512;
+ else
+ screen->group_bytes = 256;
+
screen->cpp = dri_priv->bpp / 8;
screen->AGPMode = dri_priv->AGPMode;
else
screen->chip_flags |= RADEON_CLASS_R600;
- /* r6xx+ tiling, default to 256 group bytes */
- screen->group_bytes = 256;
- if (IS_R600_CLASS(screen) && (sPriv->drm_version.minor >= 6)) {
- ret = radeonGetParam(sPriv, RADEON_INFO_TILE_CONFIG, &temp);
- if (ret)
- fprintf(stderr, "failed to get tiling info\n");
- else {
- screen->tile_config = temp;
- screen->r7xx_bank_op = 0;
- switch((screen->tile_config & 0xe) >> 1) {
- case 0:
- screen->num_channels = 1;
- break;
- case 1:
- screen->num_channels = 2;
- break;
- case 2:
- screen->num_channels = 4;
- break;
- case 3:
- screen->num_channels = 8;
- break;
- default:
- fprintf(stderr, "bad channels\n");
- break;
- }
- switch((screen->tile_config & 0x30) >> 4) {
- case 0:
- screen->num_banks = 4;
- break;
- case 1:
- screen->num_banks = 8;
- break;
- default:
- fprintf(stderr, "bad banks\n");
- break;
+ /* r6xx+ tiling, default group bytes */
+ if (screen->chip_family >= CHIP_FAMILY_CEDAR)
+ screen->group_bytes = 512;
+ else
+ screen->group_bytes = 256;
+ if (IS_R600_CLASS(screen)) {
+ if ((sPriv->drm_version.minor >= 6) &&
+ (screen->chip_family < CHIP_FAMILY_CEDAR)) {
+ ret = radeonGetParam(sPriv, RADEON_INFO_TILE_CONFIG, &temp);
+ if (ret)
+ fprintf(stderr, "failed to get tiling info\n");
+ else {
+ screen->tile_config = temp;
+ screen->r7xx_bank_op = 0;
+ switch ((screen->tile_config & 0xe) >> 1) {
+ case 0:
+ screen->num_channels = 1;
+ break;
+ case 1:
+ screen->num_channels = 2;
+ break;
+ case 2:
+ screen->num_channels = 4;
+ break;
+ case 3:
+ screen->num_channels = 8;
+ break;
+ default:
+ fprintf(stderr, "bad channels\n");
+ break;
+ }
+ switch ((screen->tile_config & 0x30) >> 4) {
+ case 0:
+ screen->num_banks = 4;
+ break;
+ case 1:
+ screen->num_banks = 8;
+ break;
+ default:
+ fprintf(stderr, "bad banks\n");
+ break;
+ }
+ switch ((screen->tile_config & 0xc0) >> 6) {
+ case 0:
+ screen->group_bytes = 256;
+ break;
+ case 1:
+ screen->group_bytes = 512;
+ break;
+ default:
+ fprintf(stderr, "bad group_bytes\n");
+ break;
+ }
}
- switch((screen->tile_config & 0xc0) >> 6) {
- case 0:
- screen->group_bytes = 256;
- break;
- case 1:
- screen->group_bytes = 512;
- break;
- default:
- fprintf(stderr, "bad group_bytes\n");
- break;
+ } else if ((sPriv->drm_version.minor >= 7) &&
+ (screen->chip_family >= CHIP_FAMILY_CEDAR)) {
+ ret = radeonGetParam(sPriv, RADEON_INFO_TILE_CONFIG, &temp);
+ if (ret)
+ fprintf(stderr, "failed to get tiling info\n");
+ else {
+ screen->tile_config = temp;
+ screen->r7xx_bank_op = 0;
+ switch (screen->tile_config & 0xf) {
+ case 0:
+ screen->num_channels = 1;
+ break;
+ case 1:
+ screen->num_channels = 2;
+ break;
+ case 2:
+ screen->num_channels = 4;
+ break;
+ case 3:
+ screen->num_channels = 8;
+ break;
+ default:
+ fprintf(stderr, "bad channels\n");
+ break;
+ }
+ switch ((screen->tile_config & 0xf0) >> 4) {
+ case 0:
+ screen->num_banks = 4;
+ break;
+ case 1:
+ screen->num_banks = 8;
+ break;
+ case 2:
+ screen->num_banks = 16;
+ break;
+ default:
+ fprintf(stderr, "bad banks\n");
+ break;
+ }
+ switch ((screen->tile_config & 0xf00) >> 8) {
+ case 0:
+ screen->group_bytes = 256;
+ break;
+ case 1:
+ screen->group_bytes = 512;
+ break;
+ default:
+ fprintf(stderr, "bad group_bytes\n");
+ break;
+ }
}
}
}
projects / mesa.git / blobdiff