Reduce noiseness of the driver.

[mesa.git] / src / mesa / drivers / dri / radeon / radeon_screen.c

diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c
index a3b2047bc8e1225b845ab939b816062d2813d21e..9687b7efac1680dedb2e05bbaf63b90077ef2b26 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -54,17 +54,19 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  */
 #include "xmlpool.h"
 
-const char __driConfigOptions[] =
+PUBLIC const char __driConfigOptions[] =
 DRI_CONF_BEGIN
     DRI_CONF_SECTION_PERFORMANCE
         DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
         DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
         DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
+        DRI_CONF_HYPERZ(false)
     DRI_CONF_SECTION_END
     DRI_CONF_SECTION_QUALITY
         DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
         DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
         DRI_CONF_NO_NEG_LOD_BIAS(false)
+        DRI_CONF_FORCE_S3TC_ENABLE(false)
         DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
         DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
         DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
@@ -73,7 +75,7 @@ DRI_CONF_BEGIN
         DRI_CONF_NO_RAST(false)
     DRI_CONF_SECTION_END
 DRI_CONF_END;
-static const GLuint __driNConfigOptions = 10;
+static const GLuint __driNConfigOptions = 12;
 
 #if 1
 /* Including xf86PciInfo.h introduces a bunch of errors...
@@ -87,11 +89,14 @@ static const GLuint __driNConfigOptions = 10;
 #define PCI_CHIP_RADEON_QZ     0x515A
 
 #define PCI_CHIP_RADEON_LW     0x4C57 /* mobility 7 - has tcl */
+#define PCI_CHIP_RADEON_LX     0x4C58 /* mobility FireGL 7800 m7 */
 
 #define PCI_CHIP_RADEON_LY     0x4C59
 #define PCI_CHIP_RADEON_LZ     0x4C5A
 
 #define PCI_CHIP_RV200_QW      0x5157 /* Radeon 7500 - not an R200 at all */
+#define PCI_CHIP_RV200_QX      0x5158
+
 /* IGP Chipsets */
 #define PCI_CHIP_RS100_4136     0x4136
 #define PCI_CHIP_RS200_4137     0x4137
@@ -129,8 +134,8 @@ radeonFillInModes( unsigned pixel_bits, unsigned depth_bits,
        GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
     };
 
-    uint8_t depth_bits_array[2];
-    uint8_t stencil_bits_array[2];
+    u_int8_t depth_bits_array[2];
+    u_int8_t stencil_bits_array[2];
 
 
     depth_bits_array[0] = depth_bits;
@@ -268,7 +273,7 @@ radeonScreenPtr radeonCreateScreen( __DRIscreenPrivate *sPriv )
       __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
       return NULL;
    }
-   screen->scratch = (__volatile__ uint32_t *)
+   screen->scratch = (__volatile__ u_int32_t *)
       ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
 
    screen->buffers = drmMapBufs( sPriv->fd );
@@ -308,8 +313,12 @@ radeonScreenPtr radeonCreateScreen( __DRIscreenPrivate *sPriv )
    case PCI_CHIP_RADEON_QE:
    case PCI_CHIP_RADEON_QF:
    case PCI_CHIP_RADEON_QG:
+      /* all original radeons (7200) presumably have a stencil op bug */
+      screen->chipset |= RADEON_CHIPSET_BROKEN_STENCIL;
    case PCI_CHIP_RV200_QW:
+   case PCI_CHIP_RV200_QX:
    case PCI_CHIP_RADEON_LW:
+   case PCI_CHIP_RADEON_LX:
       screen->chipset |= RADEON_CHIPSET_TCL;
    case PCI_CHIP_RADEON_QY:
    case PCI_CHIP_RADEON_QZ:
@@ -346,6 +355,10 @@ radeonScreenPtr radeonCreateScreen( __DRIscreenPrivate *sPriv )
    screen->depthOffset = dri_priv->depthOffset;
    screen->depthPitch  = dri_priv->depthPitch;
 
+   /* Check if ddx has set up a surface reg to cover depth buffer */
+   screen->depthHasSurface = ((sPriv->ddxMajor > 4) &&
+      (screen->chipset & RADEON_CHIPSET_TCL));
+
    screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
                                       + screen->fbLocation;
    screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
@@ -516,6 +529,7 @@ void *__driCreateScreen(Display *dpy, int scrn, __DRIscreen *psc,
  *         failure.
  */
 #ifdef USE_NEW_INTERFACE
+PUBLIC
 void * __driCreateNewScreen( __DRInativeDisplay *dpy, int scrn, __DRIscreen *psc,
                             const __GLcontextModes * modes,
                             const __DRIversion * ddx_version,
@@ -528,11 +542,11 @@ void * __driCreateNewScreen( __DRInativeDisplay *dpy, int scrn, __DRIscreen *psc
 
 {
    __DRIscreenPrivate *psp;
-   static const __DRIversion ddx_expected = { 4, 0, 0 };
+   static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
    static const __DRIversion dri_expected = { 4, 0, 0 };
    static const __DRIversion drm_expected = { 1, 3, 0 };
 
-   if ( ! driCheckDriDdxDrmVersions2( "Radeon",
+   if ( ! driCheckDriDdxDrmVersions3( "Radeon",
                                      dri_version, & dri_expected,
                                      ddx_version, & ddx_expected,
                                      drm_version, & drm_expected ) ) {