intel: fix the gen 11 compute shader scratch IDs

[mesa.git] / src / mesa / drivers / dri / radeon / radeon_screen.c

diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c
index 5637361a91655797dbb9c43e6ad14c317ff20947..cde35d3abf6047909666a7509375d616efc7274a 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -75,6 +75,31 @@ DRI_CONF_OPT_BEGIN_V(texture_units,int,def, # min ":" # max ) \
         DRI_CONF_DESC(en,"Number of texture units used") \
 DRI_CONF_OPT_END
 
+#define DRI_CONF_HYPERZ(def) \
+DRI_CONF_OPT_BEGIN_B(hyperz, def) \
+        DRI_CONF_DESC(en,"Use HyperZ to boost performance") \
+DRI_CONF_OPT_END
+
+#define DRI_CONF_TCL_MODE(def) \
+DRI_CONF_OPT_BEGIN_V(tcl_mode,enum,def,"0:3") \
+        DRI_CONF_DESC_BEGIN(en,"TCL mode (Transformation, Clipping, Lighting)") \
+                DRI_CONF_ENUM(0,"Use software TCL pipeline") \
+                DRI_CONF_ENUM(1,"Use hardware TCL as first TCL pipeline stage") \
+                DRI_CONF_ENUM(2,"Bypass the TCL pipeline") \
+                DRI_CONF_ENUM(3,"Bypass the TCL pipeline with state-based machine code generated on-the-fly") \
+        DRI_CONF_DESC_END \
+DRI_CONF_OPT_END
+
+#define DRI_CONF_NO_NEG_LOD_BIAS(def) \
+DRI_CONF_OPT_BEGIN_B(no_neg_lod_bias, def) \
+        DRI_CONF_DESC(en,"Forbid negative texture LOD bias") \
+DRI_CONF_OPT_END
+
+#define DRI_CONF_DEF_MAX_ANISOTROPY(def,range) \
+DRI_CONF_OPT_BEGIN_V(def_max_anisotropy,float,def,range) \
+        DRI_CONF_DESC(en,"Initial maximum value for anisotropic texture filtering") \
+DRI_CONF_OPT_END
+
 #if defined(RADEON_R100)       /* R100 */
 static const __DRIconfigOptionsExtension radeon_config_options = {
    .base = { __DRI_CONFIG_OPTIONS, 1 },
@@ -671,11 +696,26 @@ radeonCreateBuffer( __DRIscreen *driScrnPriv,
     _mesa_initialize_window_framebuffer(&rfb->base, mesaVis);
 
     if (mesaVis->redBits == 5)
-        rgbFormat = _mesa_little_endian() ? MESA_FORMAT_B5G6R5_UNORM : MESA_FORMAT_R5G6B5_UNORM;
+        rgbFormat =
+#if UTIL_ARCH_LITTLE_ENDIAN
+           MESA_FORMAT_B5G6R5_UNORM;
+#else
+           MESA_FORMAT_R5G6B5_UNORM;
+#endif
     else if (mesaVis->alphaBits == 0)
-        rgbFormat = _mesa_little_endian() ? MESA_FORMAT_B8G8R8X8_UNORM : MESA_FORMAT_X8R8G8B8_UNORM;
+        rgbFormat =
+#if UTIL_ARCH_LITTLE_ENDIAN
+           MESA_FORMAT_B8G8R8X8_UNORM;
+#else
+           MESA_FORMAT_X8R8G8B8_UNORM;
+#endif
     else
-        rgbFormat = _mesa_little_endian() ? MESA_FORMAT_B8G8R8A8_UNORM : MESA_FORMAT_A8R8G8B8_UNORM;
+        rgbFormat = 
+#if UTIL_ARCH_LITTLE_ENDIAN
+           MESA_FORMAT_B8G8R8A8_UNORM;
+#else
+           MESA_FORMAT_A8R8G8B8_UNORM;
+#endif
 
     /* front color renderbuffer */
     rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);