drmAddress map; /* Mapping of the DRM region */
} radeonRegionRec, *radeonRegionPtr;
-typedef struct {
+typedef struct radeon_screen {
int chip_family;
int chip_flags;
int cpp;
drmBufMapPtr buffers;
- __volatile__ u_int32_t *scratch;
+ __volatile__ uint32_t *scratch;
__DRIscreenPrivate *driScreen;
unsigned int sarea_priv_offset;
/* Configuration cache with default values for all contexts */
driOptionCache optionCache;
+
+ const __DRIextension *extensions[16];
+
+ int num_gb_pipes;
+ int kernel_mm;
+ drm_radeon_sarea_t *sarea; /* Private SAREA data */
+ struct radeon_bo_manager *bom;
} radeonScreenRec, *radeonScreenPtr;
#define IS_R100_CLASS(screen) \