radeon: emit scissor when using cs path

[mesa.git] / src / mesa / drivers / dri / radeon / radeon_span.c

diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c
index 3d2c5da4c0655ad34f632d2764e3821634fd13b8..e28f28662b458da7b15a587e8862e2f965236c7f 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_span.c
+++ b/src/mesa/drivers/dri/radeon/radeon_span.c
@@ -178,6 +178,19 @@ static GLubyte *radeon_ptr(const struct radeon_renderbuffer * rrb,
     return &ptr[offset];
 }
 
+#ifndef COMPILE_R300
+static uint32_t
+z24s8_to_s8z24(uint32_t val)
+{
+   return (val << 24) | (val >> 8);
+}
+
+static uint32_t
+s8z24_to_z24s8(uint32_t val)
+{
+   return (val >> 24) | (val << 8);
+}
+#endif
 
 /*
  * Note that all information needed to access pixels in a renderbuffer
@@ -248,7 +261,11 @@ static GLubyte *radeon_ptr(const struct radeon_renderbuffer * rrb,
 
 #define TAG(x)    radeon##x##_xRGB8888
 #define TAG2(x,y) radeon##x##_xRGB8888##y
-#define GET_PTR(X,Y) radeon_ptr32(rrb, (X) + x_off, (Y) + y_off)
+#define GET_VALUE(_x, _y) ((*(GLuint*)(radeon_ptr32(rrb, _x + x_off, _y + y_off)) | 0xff000000))
+#define PUT_VALUE(_x, _y, d) { \
+   GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x + x_off, _y + y_off );                \
+   *_ptr = d;                                                          \
+} while (0)
 #include "spantmp2.h"
 
 /* 32 bit, ARGB8888 color spanline and pixel functions
@@ -288,7 +305,7 @@ static GLubyte *radeon_ptr(const struct radeon_renderbuffer * rrb,
 #define TAG(x) radeon##x##_z16
 #include "depthtmp.h"
 
-/* 24 bit depth, 8 bit stencil depthbuffer functions
+/* 24 bit depth
  *
  * Careful: It looks like the R300 uses ZZZS byte order while the R200
  * uses SZZZ for 24 bit depth, 8 bit stencil mode.
@@ -317,12 +334,52 @@ do {                                                                      \
 
 #ifdef COMPILE_R300
 #define READ_DEPTH( d, _x, _y )                                                \
-  do { \
+  do {                                                                 \
     d = (*(GLuint*)(radeon_ptr32(rrb, _x + x_off, _y + y_off)) & 0xffffff00) >> 8; \
   }while(0)
 #else
+#define READ_DEPTH( d, _x, _y )        \
+  d = *(GLuint*)(radeon_ptr32(rrb, _x + x_off, _y + y_off)) & 0x00ffffff;
+#endif
+/*
+    fprintf(stderr, "dval(%d, %d, %d, %d)=0x%08X\n", _x, xo, _y, yo, d);\
+   d = *(GLuint*)(radeon_ptr(rrb, _x,  _y )) & 0x00ffffff;
+*/
+#define TAG(x) radeon##x##_z24
+#include "depthtmp.h"
+
+/* 24 bit depth, 8 bit stencil depthbuffer functions
+ * EXT_depth_stencil
+ *
+ * Careful: It looks like the R300 uses ZZZS byte order while the R200
+ * uses SZZZ for 24 bit depth, 8 bit stencil mode.
+ */
+#define VALUE_TYPE GLuint
+
+#ifdef COMPILE_R300
+#define WRITE_DEPTH( _x, _y, d )                                       \
+do {                                                                   \
+   GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x + x_off, _y + y_off );                \
+   *_ptr = d;                                                          \
+} while (0)
+#else
+#define WRITE_DEPTH( _x, _y, d )                                       \
+do {                                                                   \
+   GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x + x_off, _y + y_off );        \
+   GLuint tmp = z24s8_to_s8z24(d);                                     \
+   *_ptr = tmp;                                        \
+} while (0)
+#endif
+
+#ifdef COMPILE_R300
 #define READ_DEPTH( d, _x, _y )                                                \
-   d = *(GLuint*)(radeon_ptr32(rrb, _x + x_off,        _y + y_off )) & 0x00ffffff;
+  do { \
+    d = (*(GLuint*)(radeon_ptr32(rrb, _x + x_off, _y + y_off)));       \
+  }while(0)
+#else
+#define READ_DEPTH( d, _x, _y )        do {                                    \
+    d = s8z24_to_z24s8(*(GLuint*)(radeon_ptr32(rrb, _x + x_off,        _y + y_off ))); \
+  } while (0)
 #endif
 /*
     fprintf(stderr, "dval(%d, %d, %d, %d)=0x%08X\n", _x, xo, _y, yo, d);\
@@ -377,7 +434,7 @@ do {                                                                        \
 #include "stenciltmp.h"
 
 
-void map_unmap_rb(struct gl_renderbuffer *rb, int flag)
+static void map_unmap_rb(struct gl_renderbuffer *rb, int flag)
 {
        struct radeon_renderbuffer *rrb = radeon_renderbuffer(rb);
        int r;
@@ -403,7 +460,6 @@ void map_unmap_rb(struct gl_renderbuffer *rb, int flag)
 static void
 radeon_map_unmap_buffers(GLcontext *ctx, GLboolean map)
 {
-       radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
        GLuint i, j;
 
        /* color draw buffers */
@@ -442,6 +498,15 @@ static void radeonSpanRenderStart(GLcontext * ctx)
 
        radeon_firevertices(rmesa);
 
+       /* The locking and wait for idle should really only be needed in classic mode.
+        * In a future memory manager based implementation, this should become
+        * unnecessary due to the fact that mapping our buffers, textures, etc.
+        * should implicitly wait for any previous rendering commands that must
+        * be waited on. */
+       if (!rmesa->radeonScreen->driScreen->dri2.enabled) {
+               LOCK_HARDWARE(rmesa);
+               radeonWaitForIdleLocked(rmesa);
+       }
        for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
                if (ctx->Texture.Unit[i]._ReallyEnabled)
                        ctx->Driver.MapTexture(ctx, ctx->Texture.Unit[i]._Current);
@@ -449,13 +514,8 @@ static void radeonSpanRenderStart(GLcontext * ctx)
 
        radeon_map_unmap_buffers(ctx, 1);
 
-       /* The locking and wait for idle should really only be needed in classic mode.
-        * In a future memory manager based implementation, this should become
-        * unnecessary due to the fact that mapping our buffers, textures, etc.
-        * should implicitly wait for any previous rendering commands that must
-        * be waited on. */
-       LOCK_HARDWARE(rmesa);
-       radeonWaitForIdleLocked(rmesa);
+
+
 }
 
 static void radeonSpanRenderFinish(GLcontext * ctx)
@@ -463,8 +523,9 @@ static void radeonSpanRenderFinish(GLcontext * ctx)
        radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
        int i;
        _swrast_flush(ctx);
-       UNLOCK_HARDWARE(rmesa);
-
+       if (!rmesa->radeonScreen->driScreen->dri2.enabled) {
+               UNLOCK_HARDWARE(rmesa);
+       }
        for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) {
                if (ctx->Texture.Unit[i]._ReallyEnabled)
                        ctx->Driver.UnmapTexture(ctx, ctx->Texture.Unit[i]._Current);
@@ -495,9 +556,9 @@ static void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb)
        } else if (rrb->base._ActualFormat == GL_DEPTH_COMPONENT16) {
                radeonInitDepthPointers_z16(&rrb->base);
        } else if (rrb->base._ActualFormat == GL_DEPTH_COMPONENT24) {
-               radeonInitDepthPointers_z24_s8(&rrb->base);
+               radeonInitDepthPointers_z24(&rrb->base);
        } else if (rrb->base._ActualFormat == GL_DEPTH24_STENCIL8_EXT) {
-               radeonInitStencilPointers_z24_s8(&rrb->base);
+               radeonInitDepthPointers_z24_s8(&rrb->base);
        } else if (rrb->base._ActualFormat == GL_STENCIL_INDEX8_EXT) {
                radeonInitStencilPointers_z24_s8(&rrb->base);
        }