Merge branch '7.8'

[mesa.git] / src / mesa / drivers / dri / radeon / radeon_state.c

diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c
index ec5612fdd7f9f0702ea2d67f7e22effdc505abd9..539b067742fda0b588a0b13fe98af4d343547f55 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_state.c
+++ b/src/mesa/drivers/dri/radeon/radeon_state.c
@@ -1901,7 +1901,7 @@ void radeonUploadTexMatrix( r100ContextPtr rmesa,
    So: if we need the q coord in the end (solely determined by the texture
    target, i.e. 2d / 1d / texrect targets) we swap the third and 4th row.
    Additionally, if we don't have texgen but 4 tex coords submitted, we swap
-   column 3 and 4 (for the 2d / 1d / texrect targets) since the the q coord
+   column 3 and 4 (for the 2d / 1d / texrect targets) since the q coord
    will get submitted in the "wrong", i.e. 3rd, slot.
    If an app submits 3 coords for 2d targets, we assume it is saving on vertex
    size and using the texture matrix to swap the r and q coords around (ut2k3
@@ -2251,7 +2251,8 @@ void radeonInitStateFuncs( GLcontext *ctx , GLboolean dri2 )
    ctx->Driver.ReadBuffer              = radeonReadBuffer;
    ctx->Driver.CopyPixels               = _mesa_meta_CopyPixels;
    ctx->Driver.DrawPixels               = _mesa_meta_DrawPixels;
-   ctx->Driver.ReadPixels               = radeonReadPixels;
+   if (dri2)
+          ctx->Driver.ReadPixels               = radeonReadPixels;
 
    ctx->Driver.AlphaFunc               = radeonAlphaFunc;
    ctx->Driver.BlendEquationSeparate   = radeonBlendEquationSeparate;