radeon/r200/r300: another big merge upheavel.

[mesa.git] / src / mesa / drivers / dri / radeon / radeon_state.c

diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c
index 6ffc84848095d5aa2bcd205382618797e91a0e5e..a9ec1d51c7e8255970ed6c78fbdbbde2801572fa 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_state.c
+++ b/src/mesa/drivers/dri/radeon/radeon_state.c
@@ -47,6 +47,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "swrast_setup/swrast_setup.h"
 
 #include "radeon_context.h"
+#include "common_cmdbuf.h"
 #include "radeon_ioctl.h"
 #include "radeon_state.h"
 #include "radeon_tcl.h"
@@ -406,23 +407,6 @@ static void radeonFogfv( GLcontext *ctx, GLenum pname, const GLfloat *param )
    }
 }
 
-
-/* =============================================================
- * Scissoring
- */
-static void radeonScissor( GLcontext *ctx,
-                          GLint x, GLint y, GLsizei w, GLsizei h )
-{
-   r100ContextPtr rmesa = R100_CONTEXT(ctx);
-
-   if ( ctx->Scissor.Enabled ) {
-      RADEON_FIREVERTICES( rmesa );    /* don't pipeline cliprect changes */
-      radeonUpdateScissor( ctx );
-   }
-
-}
-
-
 /* =============================================================
  * Culling
  */
@@ -567,7 +551,7 @@ static void radeonPolygonStipple( GLcontext *ctx, const GLubyte *mask )
 
    /* TODO: push this into cmd mechanism
     */
-   RADEON_FIREVERTICES( rmesa );
+   radeon_firevertices(&rmesa->radeon);
    LOCK_HARDWARE( &rmesa->radeon );
 
    /* FIXME: Use window x,y offsets into stipple RAM.
@@ -1415,7 +1399,7 @@ void radeonUpdateWindow( GLcontext *ctx )
    float_ui32_type sz = { v[MAT_SZ] * rmesa->radeon.state.depth.scale };
    float_ui32_type tz = { v[MAT_TZ] * rmesa->radeon.state.depth.scale };
 
-   RADEON_FIREVERTICES( rmesa );
+   radeon_firevertices(&rmesa->radeon);
    RADEON_STATECHANGE( rmesa, vpt );
 
    rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE]  = sx.ui32;
@@ -1561,7 +1545,7 @@ static void radeonDrawBuffer( GLcontext *ctx, GLenum mode )
       fprintf(stderr, "%s %s\n", __FUNCTION__,
              _mesa_lookup_enum_by_nr( mode ));
 
-   RADEON_FIREVERTICES(rmesa); /* don't pipeline cliprect changes */
+   radeon_firevertices(&rmesa->radeon);        /* don't pipeline cliprect changes */
 
    if (ctx->DrawBuffer->_NumColorDrawBuffers != 1) {
       /* 0 (GL_NONE) buffers or multiple color drawing buffers */
@@ -1843,7 +1827,7 @@ static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state )
    }
 
    case GL_SCISSOR_TEST:
-      RADEON_FIREVERTICES( rmesa );
+      radeon_firevertices(&rmesa->radeon);
       rmesa->radeon.state.scissor.enabled = state;
       radeonUpdateScissor( ctx );
       break;
@@ -2060,8 +2044,6 @@ static void update_texturematrix( GLcontext *ctx )
 
    tpc = (texMatEnabled | rmesa->TexGenEnabled);
 
-   fprintf(stderr,"setting tpc to %x %x\n", tpc, rmesa->TexGenEnabled);
-
    /* TCL_TEX_COMPUTED_x is TCL_TEX_INPUT_x | 0x8 */
    vs &= ~((RADEON_TCL_TEX_COMPUTED_TEX_0 << RADEON_TCL_TEX_0_OUTPUT_SHIFT) |
           (RADEON_TCL_TEX_COMPUTED_TEX_0 << RADEON_TCL_TEX_1_OUTPUT_SHIFT) |