i965/vec4: Assert that ATTR regions are register-aligned.

[mesa.git] / src / mesa / drivers / dri / radeon / radeon_state.h

diff --git a/src/mesa/drivers/dri/radeon/radeon_state.h b/src/mesa/drivers/dri/radeon/radeon_state.h
index cb98969c492f4107e8c4663036446710fd017088..2ff5e427ae0a31f60daa7146609ae81f16890a40 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_state.h
+++ b/src/mesa/drivers/dri/radeon/radeon_state.h
@@ -44,19 +44,19 @@ extern void radeonInitStateFuncs( struct gl_context *ctx );
 
 extern void radeonUpdateMaterial( struct gl_context *ctx );
 
-extern void radeonUpdateViewportOffset( struct gl_context *ctx );
 extern void radeonUpdateWindow( struct gl_context *ctx );
 extern void radeonUpdateDrawBuffer( struct gl_context *ctx );
 extern void radeonUploadTexMatrix( r100ContextPtr rmesa,
                                   int unit, GLboolean swapcols );
 
+extern GLboolean r100ValidateBuffers(struct gl_context *ctx);
 extern GLboolean radeonValidateState( struct gl_context *ctx );
 
 
 extern void radeonFallback( struct gl_context *ctx, GLuint bit, GLboolean mode );
 #define FALLBACK( rmesa, bit, mode ) do {                              \
    if ( 0 ) fprintf( stderr, "FALLBACK in %s: #%d=%d\n",               \
-                    __FUNCTION__, bit, mode );                         \
+                    __func__, bit, mode );                             \
    radeonFallback( &rmesa->radeon.glCtx, bit, mode );                          \
 } while (0)