fixup pci code for Jon's last checkin for changing page size
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_state_init.c
index 0b2a1089b8cd1b5c10b0b844de496117737ba8bd..1dece862088b22ed4c40c040723cc61e036a88f3 100644 (file)
@@ -46,6 +46,8 @@
 #include "radeon_swtcl.h"
 #include "radeon_vtxfmt.h"
 
+#include "xmlpool.h"
+
 /* =============================================================
  * State initialization
  */
@@ -57,8 +59,9 @@ void radeonPrintDirty( radeonContextPtr rmesa, const char *msg )
    fprintf(stderr, msg);
    fprintf(stderr, ": ");
 
-   foreach(l, &(rmesa->hw.dirty)) {
-      fprintf(stderr, "%s, ", l->name);
+   foreach(l, &rmesa->hw.atomlist) {
+      if (l->dirty || rmesa->hw.all_dirty)
+        fprintf(stderr, "%s, ", l->name);
    }
 
    fprintf(stderr, "\n");
@@ -66,7 +69,7 @@ void radeonPrintDirty( radeonContextPtr rmesa, const char *msg )
 
 static int cmdpkt( int id ) 
 {
-   drmRadeonCmdHeader h;
+   drm_radeon_cmd_header_t h;
    h.i = 0;
    h.packet.cmd_type = RADEON_CMD_PACKET;
    h.packet.packet_id = id;
@@ -75,7 +78,7 @@ static int cmdpkt( int id )
 
 static int cmdvec( int offset, int stride, int count ) 
 {
-   drmRadeonCmdHeader h;
+   drm_radeon_cmd_header_t h;
    h.i = 0;
    h.vectors.cmd_type = RADEON_CMD_VECTORS;
    h.vectors.offset = offset;
@@ -86,7 +89,7 @@ static int cmdvec( int offset, int stride, int count )
 
 static int cmdscl( int offset, int stride, int count ) 
 {
-   drmRadeonCmdHeader h;
+   drm_radeon_cmd_header_t h;
    h.i = 0;
    h.scalars.cmd_type = RADEON_CMD_SCALARS;
    h.scalars.offset = offset;
@@ -171,7 +174,7 @@ void radeonInitState( radeonContextPtr rmesa )
       rmesa->state.depth.clear = 0x00ffffff;
       rmesa->state.depth.scale = 1.0 / (GLfloat)0xffffff;
       depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
-      rmesa->state.stencil.clear = 0xff000000;
+      rmesa->state.stencil.clear = 0xffff0000;
       break;
    default:
       fprintf( stderr, "Error: Unsupported depth %d... exiting\n",
@@ -195,11 +198,7 @@ void radeonInitState( radeonContextPtr rmesa )
    rmesa->state.pixel.readOffset = rmesa->state.color.drawOffset;
    rmesa->state.pixel.readPitch  = rmesa->state.color.drawPitch;
 
-   /* Initialize lists:
-    */
-   make_empty_list(&(rmesa->hw.dirty));
-   make_empty_list(&(rmesa->hw.clean));
-
+   rmesa->hw.max_state_size = 0;
 
 #define ALLOC_STATE( ATOM, CHK, SZ, NM, FLAG )                         \
    do {                                                                \
@@ -209,7 +208,8 @@ void radeonInitState( radeonContextPtr rmesa )
       rmesa->hw.ATOM.name = NM;                                        \
       rmesa->hw.ATOM.is_tcl = FLAG;                                    \
       rmesa->hw.ATOM.check = check_##CHK;                              \
-      insert_at_head(&(rmesa->hw.dirty), &(rmesa->hw.ATOM));   \
+      rmesa->hw.ATOM.dirty = GL_TRUE;                          \
+      rmesa->hw.max_state_size += SZ * sizeof(int);            \
    } while (0)
       
       
@@ -252,6 +252,7 @@ void radeonInitState( radeonContextPtr rmesa )
    ALLOC_STATE( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0 );
    ALLOC_STATE( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0 );
 
+   radeonSetUpAtomList( rmesa );
 
    /* Fill in the packet headers:
     */
@@ -322,12 +323,15 @@ void radeonInitState( radeonContextPtr rmesa )
                                            RADEON_DST_BLEND_GL_ZERO );
 
    rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] =
-      rmesa->radeonScreen->depthOffset;
+      rmesa->radeonScreen->depthOffset + rmesa->radeonScreen->fbLocation;
 
    rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] = 
       ((rmesa->radeonScreen->depthPitch &
        RADEON_DEPTHPITCH_MASK) |
        RADEON_DEPTH_ENDIAN_NO_SWAP);
+       
+   if (rmesa->using_hyperz)
+       rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= RADEON_DEPTH_HYPERZ;
 
    rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (depth_fmt |
                                               RADEON_Z_TEST_LESS |
@@ -337,6 +341,17 @@ void radeonInitState( radeonContextPtr rmesa )
                                               RADEON_STENCIL_ZFAIL_KEEP |
                                               RADEON_Z_WRITE_ENABLE);
 
+   if (rmesa->using_hyperz) {
+       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_COMPRESSION_ENABLE |
+                                                  RADEON_Z_DECOMPRESSION_ENABLE;
+      if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL) {
+        /* works for q3, but slight rendering errors with glxgears ? */
+/*      rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
+        /* need this otherwise get lots of lockups with q3 ??? */
+        rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_FORCE_Z_DIRTY;
+      } 
+   }
+
    rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (RADEON_SCISSOR_ENABLE |
                                     RADEON_ANTI_ALIAS_NONE);
 
@@ -344,10 +359,28 @@ void radeonInitState( radeonContextPtr rmesa )
                                       color_fmt |
                                       (1<<15));
 
-   rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |=  RADEON_DITHER_ENABLE;
-
-   rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = (rmesa->state.color.drawOffset &
-                                             RADEON_COLOROFFSET_MASK);
+   switch ( driQueryOptioni( &rmesa->optionCache, "dither_mode" ) ) {
+   case DRI_CONF_DITHER_XERRORDIFFRESET:
+      rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_INIT;
+      break;
+   case DRI_CONF_DITHER_ORDERED:
+      rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_SCALE_DITHER_ENABLE;
+      break;
+   }
+   if ( driQueryOptioni( &rmesa->optionCache, "round_mode" ) ==
+       DRI_CONF_ROUND_ROUND )
+      rmesa->state.color.roundEnable = RADEON_ROUND_ENABLE;
+   else
+      rmesa->state.color.roundEnable = 0;
+   if ( driQueryOptioni (&rmesa->optionCache, "color_reduction" ) ==
+       DRI_CONF_COLOR_REDUCTION_DITHER )
+      rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE;
+   else
+      rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->state.color.roundEnable;
+
+   rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((rmesa->state.color.drawOffset +
+                                              rmesa->radeonScreen->fbLocation)
+                                             & RADEON_COLOROFFSET_MASK);
 
    rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((rmesa->state.color.drawPitch &
                                              RADEON_COLORPITCH_MASK) |
@@ -421,8 +454,9 @@ void radeonInitState( radeonContextPtr rmesa )
           (2 << RADEON_TXFORMAT_WIDTH_SHIFT) |
           (2 << RADEON_TXFORMAT_HEIGHT_SHIFT));
 
-      /* FIXME: What is this magic value? */
-      rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] = 0x2000 << (2 * i);
+      /* Initialize the texture offset to the start of the card texture heap */
+      rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] =
+         rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
 
       rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
       rmesa->hw.tex[i].cmd[TEX_PP_TXCBLEND] =  
@@ -478,10 +512,10 @@ void radeonInitState( radeonContextPtr rmesa )
       (RADEON_SPECULAR_LIGHTS |
        RADEON_DIFFUSE_SPECULAR_COMBINE |
        RADEON_LOCAL_LIGHT_VEC_GL |
-       (RADEON_LM_SOURCE_STATE_PREMULT << RADEON_EMISSIVE_SOURCE_SHIFT) |
-       (RADEON_LM_SOURCE_STATE_PREMULT << RADEON_AMBIENT_SOURCE_SHIFT) |
-       (RADEON_LM_SOURCE_STATE_PREMULT << RADEON_DIFFUSE_SOURCE_SHIFT) |
-       (RADEON_LM_SOURCE_STATE_PREMULT << RADEON_SPECULAR_SOURCE_SHIFT)); 
+       (RADEON_LM_SOURCE_STATE_MULT << RADEON_EMISSIVE_SOURCE_SHIFT) |
+       (RADEON_LM_SOURCE_STATE_MULT << RADEON_AMBIENT_SOURCE_SHIFT) |
+       (RADEON_LM_SOURCE_STATE_MULT << RADEON_DIFFUSE_SOURCE_SHIFT) |
+       (RADEON_LM_SOURCE_STATE_MULT << RADEON_SPECULAR_SOURCE_SHIFT));
 
    for (i = 0 ; i < 8; i++) {
       struct gl_light *l = &ctx->Light.Light[i];
@@ -501,6 +535,7 @@ void radeonInitState( radeonContextPtr rmesa )
                           &l->LinearAttenuation );
       ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION, 
                     &l->QuadraticAttenuation );
+      *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0;
    }
 
    ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT, 
@@ -528,4 +563,6 @@ void radeonInitState( radeonContextPtr rmesa )
    rmesa->hw.eye.cmd[EYE_Y] = 0;
    rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
    rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
+   
+   rmesa->hw.all_dirty = GL_TRUE;
 }