fixup pci code for Jon's last checkin for changing page size

[mesa.git] / src / mesa / drivers / dri / radeon / radeon_state_init.c

diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c
index 7b2f14707059a586721162752aeeff8c522b0079..1dece862088b22ed4c40c040723cc61e036a88f3 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_state_init.c
+++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c
@@ -59,8 +59,9 @@ void radeonPrintDirty( radeonContextPtr rmesa, const char *msg )
    fprintf(stderr, msg);
    fprintf(stderr, ": ");
 
-   foreach(l, &(rmesa->hw.dirty)) {
-      fprintf(stderr, "%s, ", l->name);
+   foreach(l, &rmesa->hw.atomlist) {
+      if (l->dirty || rmesa->hw.all_dirty)
+        fprintf(stderr, "%s, ", l->name);
    }
 
    fprintf(stderr, "\n");
@@ -173,7 +174,7 @@ void radeonInitState( radeonContextPtr rmesa )
       rmesa->state.depth.clear = 0x00ffffff;
       rmesa->state.depth.scale = 1.0 / (GLfloat)0xffffff;
       depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
-      rmesa->state.stencil.clear = 0xff000000;
+      rmesa->state.stencil.clear = 0xffff0000;
       break;
    default:
       fprintf( stderr, "Error: Unsupported depth %d... exiting\n",
@@ -197,11 +198,6 @@ void radeonInitState( radeonContextPtr rmesa )
    rmesa->state.pixel.readOffset = rmesa->state.color.drawOffset;
    rmesa->state.pixel.readPitch  = rmesa->state.color.drawPitch;
 
-   /* Initialize lists:
-    */
-   make_empty_list(&(rmesa->hw.dirty));
-   make_empty_list(&(rmesa->hw.clean));
-
    rmesa->hw.max_state_size = 0;
 
 #define ALLOC_STATE( ATOM, CHK, SZ, NM, FLAG )                         \
@@ -212,7 +208,7 @@ void radeonInitState( radeonContextPtr rmesa )
       rmesa->hw.ATOM.name = NM;                                        \
       rmesa->hw.ATOM.is_tcl = FLAG;                                    \
       rmesa->hw.ATOM.check = check_##CHK;                              \
-      insert_at_head(&(rmesa->hw.dirty), &(rmesa->hw.ATOM));   \
+      rmesa->hw.ATOM.dirty = GL_TRUE;                          \
       rmesa->hw.max_state_size += SZ * sizeof(int);            \
    } while (0)
       
@@ -256,6 +252,7 @@ void radeonInitState( radeonContextPtr rmesa )
    ALLOC_STATE( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0 );
    ALLOC_STATE( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0 );
 
+   radeonSetUpAtomList( rmesa );
 
    /* Fill in the packet headers:
     */
@@ -332,6 +329,9 @@ void radeonInitState( radeonContextPtr rmesa )
       ((rmesa->radeonScreen->depthPitch &
        RADEON_DEPTHPITCH_MASK) |
        RADEON_DEPTH_ENDIAN_NO_SWAP);
+       
+   if (rmesa->using_hyperz)
+       rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= RADEON_DEPTH_HYPERZ;
 
    rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (depth_fmt |
                                               RADEON_Z_TEST_LESS |
@@ -341,6 +341,17 @@ void radeonInitState( radeonContextPtr rmesa )
                                               RADEON_STENCIL_ZFAIL_KEEP |
                                               RADEON_Z_WRITE_ENABLE);
 
+   if (rmesa->using_hyperz) {
+       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_COMPRESSION_ENABLE |
+                                                  RADEON_Z_DECOMPRESSION_ENABLE;
+      if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL) {
+        /* works for q3, but slight rendering errors with glxgears ? */
+/*      rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
+        /* need this otherwise get lots of lockups with q3 ??? */
+        rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_FORCE_Z_DIRTY;
+      } 
+   }
+
    rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (RADEON_SCISSOR_ENABLE |
                                     RADEON_ANTI_ALIAS_NONE);
 
@@ -552,4 +563,6 @@ void radeonInitState( radeonContextPtr rmesa )
    rmesa->hw.eye.cmd[EYE_Y] = 0;
    rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
    rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
+   
+   rmesa->hw.all_dirty = GL_TRUE;
 }