-/* $XFree86$ */
+/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_state_init.c,v 1.3 2003/02/22 06:21:11 dawes Exp $ */
/*
* Copyright 2000, 2001 VA Linux Systems Inc., Fremont, California.
*
#include "radeon_swtcl.h"
#include "radeon_vtxfmt.h"
+#include "xmlpool.h"
+
/* =============================================================
* State initialization
*/
fprintf(stderr, msg);
fprintf(stderr, ": ");
- foreach(l, &(rmesa->hw.dirty)) {
- fprintf(stderr, "%s, ", l->name);
+ foreach(l, &rmesa->hw.atomlist) {
+ if (l->dirty || rmesa->hw.all_dirty)
+ fprintf(stderr, "%s, ", l->name);
}
fprintf(stderr, "\n");
static int cmdpkt( int id )
{
- drmRadeonCmdHeader h;
+ drm_radeon_cmd_header_t h;
h.i = 0;
h.packet.cmd_type = RADEON_CMD_PACKET;
h.packet.packet_id = id;
static int cmdvec( int offset, int stride, int count )
{
- drmRadeonCmdHeader h;
+ drm_radeon_cmd_header_t h;
h.i = 0;
h.vectors.cmd_type = RADEON_CMD_VECTORS;
h.vectors.offset = offset;
static int cmdscl( int offset, int stride, int count )
{
- drmRadeonCmdHeader h;
+ drm_radeon_cmd_header_t h;
h.i = 0;
h.scalars.cmd_type = RADEON_CMD_SCALARS;
h.scalars.offset = offset;
rmesa->state.depth.clear = 0x00ffffff;
rmesa->state.depth.scale = 1.0 / (GLfloat)0xffffff;
depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
- rmesa->state.stencil.clear = 0xff000000;
+ rmesa->state.stencil.clear = 0xffff0000;
break;
default:
fprintf( stderr, "Error: Unsupported depth %d... exiting\n",
rmesa->state.pixel.readOffset = rmesa->state.color.drawOffset;
rmesa->state.pixel.readPitch = rmesa->state.color.drawPitch;
- /* Initialize lists:
- */
- make_empty_list(&(rmesa->hw.dirty));
- make_empty_list(&(rmesa->hw.clean));
-
+ rmesa->hw.max_state_size = 0;
#define ALLOC_STATE( ATOM, CHK, SZ, NM, FLAG ) \
do { \
rmesa->hw.ATOM.name = NM; \
rmesa->hw.ATOM.is_tcl = FLAG; \
rmesa->hw.ATOM.check = check_##CHK; \
- insert_at_head(&(rmesa->hw.dirty), &(rmesa->hw.ATOM)); \
+ rmesa->hw.ATOM.dirty = GL_TRUE; \
+ rmesa->hw.max_state_size += SZ * sizeof(int); \
} while (0)
ALLOC_STATE( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0 );
ALLOC_STATE( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0 );
+ radeonSetUpAtomList( rmesa );
/* Fill in the packet headers:
*/
RADEON_DST_BLEND_GL_ZERO );
rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] =
- rmesa->radeonScreen->depthOffset;
+ rmesa->radeonScreen->depthOffset + rmesa->radeonScreen->fbLocation;
rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] =
((rmesa->radeonScreen->depthPitch &
RADEON_DEPTHPITCH_MASK) |
RADEON_DEPTH_ENDIAN_NO_SWAP);
+
+ if (rmesa->using_hyperz)
+ rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= RADEON_DEPTH_HYPERZ;
rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (depth_fmt |
RADEON_Z_TEST_LESS |
RADEON_STENCIL_ZFAIL_KEEP |
RADEON_Z_WRITE_ENABLE);
+ if (rmesa->using_hyperz) {
+ rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_COMPRESSION_ENABLE |
+ RADEON_Z_DECOMPRESSION_ENABLE;
+ if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL) {
+ /* works for q3, but slight rendering errors with glxgears ? */
+/* rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
+ /* need this otherwise get lots of lockups with q3 ??? */
+ rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_FORCE_Z_DIRTY;
+ }
+ }
+
rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (RADEON_SCISSOR_ENABLE |
RADEON_ANTI_ALIAS_NONE);
color_fmt |
(1<<15));
- rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE;
-
- rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = (rmesa->state.color.drawOffset &
- RADEON_COLOROFFSET_MASK);
+ switch ( driQueryOptioni( &rmesa->optionCache, "dither_mode" ) ) {
+ case DRI_CONF_DITHER_XERRORDIFFRESET:
+ rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_INIT;
+ break;
+ case DRI_CONF_DITHER_ORDERED:
+ rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_SCALE_DITHER_ENABLE;
+ break;
+ }
+ if ( driQueryOptioni( &rmesa->optionCache, "round_mode" ) ==
+ DRI_CONF_ROUND_ROUND )
+ rmesa->state.color.roundEnable = RADEON_ROUND_ENABLE;
+ else
+ rmesa->state.color.roundEnable = 0;
+ if ( driQueryOptioni (&rmesa->optionCache, "color_reduction" ) ==
+ DRI_CONF_COLOR_REDUCTION_DITHER )
+ rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE;
+ else
+ rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->state.color.roundEnable;
+
+ rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((rmesa->state.color.drawOffset +
+ rmesa->radeonScreen->fbLocation)
+ & RADEON_COLOROFFSET_MASK);
rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((rmesa->state.color.drawPitch &
RADEON_COLORPITCH_MASK) |
(2 << RADEON_TXFORMAT_WIDTH_SHIFT) |
(2 << RADEON_TXFORMAT_HEIGHT_SHIFT));
- /* FIXME: What is this magic value? */
- rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] = 0x2000 << (2 * i);
+ /* Initialize the texture offset to the start of the card texture heap */
+ rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] =
+ rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
rmesa->hw.tex[i].cmd[TEX_PP_TXCBLEND] =
(RADEON_SPECULAR_LIGHTS |
RADEON_DIFFUSE_SPECULAR_COMBINE |
RADEON_LOCAL_LIGHT_VEC_GL |
- (RADEON_LM_SOURCE_STATE_PREMULT << RADEON_EMISSIVE_SOURCE_SHIFT) |
- (RADEON_LM_SOURCE_STATE_PREMULT << RADEON_AMBIENT_SOURCE_SHIFT) |
- (RADEON_LM_SOURCE_STATE_PREMULT << RADEON_DIFFUSE_SOURCE_SHIFT) |
- (RADEON_LM_SOURCE_STATE_PREMULT << RADEON_SPECULAR_SOURCE_SHIFT));
+ (RADEON_LM_SOURCE_STATE_MULT << RADEON_EMISSIVE_SOURCE_SHIFT) |
+ (RADEON_LM_SOURCE_STATE_MULT << RADEON_AMBIENT_SOURCE_SHIFT) |
+ (RADEON_LM_SOURCE_STATE_MULT << RADEON_DIFFUSE_SOURCE_SHIFT) |
+ (RADEON_LM_SOURCE_STATE_MULT << RADEON_SPECULAR_SOURCE_SHIFT));
for (i = 0 ; i < 8; i++) {
struct gl_light *l = &ctx->Light.Light[i];
&l->LinearAttenuation );
ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION,
&l->QuadraticAttenuation );
+ *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0;
}
ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT,
rmesa->hw.eye.cmd[EYE_Y] = 0;
rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
+
+ rmesa->hw.all_dirty = GL_TRUE;
}