r600c: add support for llano

[mesa.git] / src / mesa / drivers / dri / radeon / radeon_state_init.c

diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c
index 2d19220d8af63caa3cf0f2a1a3b60ff7fa0ded24..33b504cccf8003ea359c9422f74eef5df6bc1dd4 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_state_init.c
+++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c
@@ -33,7 +33,6 @@
 
 #include "swrast/swrast.h"
 #include "vbo/vbo.h"
-#include "tnl/tnl.h"
 #include "tnl/t_pipeline.h"
 #include "swrast_setup/swrast_setup.h"
 
@@ -41,9 +40,6 @@
 #include "radeon_mipmap_tree.h"
 #include "radeon_ioctl.h"
 #include "radeon_state.h"
-#include "radeon_tcl.h"
-#include "radeon_tex.h"
-#include "radeon_swtcl.h"
 #include "radeon_queryobj.h"
 
 #include "../r200/r200_reg.h"
@@ -199,13 +195,13 @@ static int cmdscl( int offset, int stride, int count )
 }
 
 #define CHECK( NM, FLAG, ADD )                         \
-static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom )        \
+static int check_##NM( struct gl_context *ctx, struct radeon_state_atom *atom )        \
 {                                                      \
    return FLAG ? atom->cmd_size + (ADD) : 0;                   \
 }
 
 #define TCL_CHECK( NM, FLAG, ADD )                             \
-static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom )        \
+static int check_##NM( struct gl_context *ctx, struct radeon_state_atom *atom )        \
 {                                                      \
    r100ContextPtr rmesa = R100_CONTEXT(ctx);   \
    return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
@@ -298,7 +294,7 @@ CHECK( txr2, (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_RECT_BIT), 0 )
     OUT_BATCH_TABLE((data), h.scalars.count);                          \
   } while(0)
 
-static void scl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
+static void scl_emit(struct gl_context *ctx, struct radeon_state_atom *atom)
 {
    r100ContextPtr r100 = R100_CONTEXT(ctx);
    BATCH_LOCALS(&r100->radeon);
@@ -310,7 +306,7 @@ static void scl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
 }
 
 
-static void vec_emit(GLcontext *ctx, struct radeon_state_atom *atom)
+static void vec_emit(struct gl_context *ctx, struct radeon_state_atom *atom)
 {
    r100ContextPtr r100 = R100_CONTEXT(ctx);
    BATCH_LOCALS(&r100->radeon);
@@ -322,7 +318,7 @@ static void vec_emit(GLcontext *ctx, struct radeon_state_atom *atom)
 }
 
 
-static void lit_emit(GLcontext *ctx, struct radeon_state_atom *atom)
+static void lit_emit(struct gl_context *ctx, struct radeon_state_atom *atom)
 {
    r100ContextPtr r100 = R100_CONTEXT(ctx);
    BATCH_LOCALS(&r100->radeon);
@@ -334,7 +330,7 @@ static void lit_emit(GLcontext *ctx, struct radeon_state_atom *atom)
    END_BATCH();
 }
 
-static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom)
+static void ctx_emit(struct gl_context *ctx, struct radeon_state_atom *atom)
 {
    r100ContextPtr r100 = R100_CONTEXT(ctx);
    BATCH_LOCALS(&r100->radeon);
@@ -399,7 +395,7 @@ static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom)
    END_BATCH();
 }
 
-static int check_always_ctx( GLcontext *ctx, struct radeon_state_atom *atom)
+static int check_always_ctx( struct gl_context *ctx, struct radeon_state_atom *atom)
 {
    r100ContextPtr r100 = R100_CONTEXT(ctx);
    struct radeon_renderbuffer *rrb, *drb;
@@ -421,7 +417,7 @@ static int check_always_ctx( GLcontext *ctx, struct radeon_state_atom *atom)
    return dwords;
 }
 
-static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
+static void ctx_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom)
 {
    r100ContextPtr r100 = R100_CONTEXT(ctx);
    BATCH_LOCALS(&r100->radeon);
@@ -492,7 +488,7 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
 
    if (rrb) {
      OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0));
-     OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
+     OUT_BATCH_RELOC(rrb->draw_offset, rrb->bo, rrb->draw_offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 
      OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
      OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
@@ -516,7 +512,7 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
    END_BATCH();
 }
 
-static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom)
+static void cube_emit(struct gl_context *ctx, struct radeon_state_atom *atom)
 {
    r100ContextPtr r100 = R100_CONTEXT(ctx);
    BATCH_LOCALS(&r100->radeon);
@@ -544,7 +540,7 @@ static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom)
    END_BATCH();
 }
 
-static void cube_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
+static void cube_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom)
 {
    r100ContextPtr r100 = R100_CONTEXT(ctx);
    BATCH_LOCALS(&r100->radeon);
@@ -580,7 +576,7 @@ static void cube_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
    END_BATCH();
 }
 
-static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
+static void tex_emit(struct gl_context *ctx, struct radeon_state_atom *atom)
 {
    r100ContextPtr r100 = R100_CONTEXT(ctx);
    BATCH_LOCALS(&r100->radeon);
@@ -615,7 +611,7 @@ static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
    END_BATCH();
 }
 
-static void tex_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
+static void tex_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom)
 {
    r100ContextPtr r100 = R100_CONTEXT(ctx);
    BATCH_LOCALS(&r100->radeon);
@@ -645,11 +641,11 @@ static void tex_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
      OUT_BATCH(CP_PACKET0(RADEON_PP_TXOFFSET_0 + (24 * i), 0));
      if (t->mt && !t->image_override) {
         if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) {
-            lvl = &t->mt->levels[0];
+            lvl = &t->mt->levels[t->minLod];
            OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset,
                        RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
         } else {
-           OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
+           OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, get_base_teximage_offset(t),
                     RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
         }
       } else {
@@ -670,7 +666,7 @@ static void tex_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
  */
 void radeonInitState( r100ContextPtr rmesa )
 {
-   GLcontext *ctx = rmesa->radeon.glCtx;
+   struct gl_context *ctx = rmesa->radeon.glCtx;
    GLuint i;
 
    rmesa->radeon.state.color.clear = 0x00000000;