r200: fix glean pixelFormats regression

[mesa.git] / src / mesa / drivers / dri / radeon / radeon_state_init.c

diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c
index bff16fa6aa9d661ef916d4ca4bf8262fe8e1a36c..3d0cd8d3f86472f295ac6559997b0a760bab00cb 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_state_init.c
+++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c
@@ -426,10 +426,11 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
    }
 
    /* output the first 7 bytes of context */
+   dwords = 10;
    if (drb)
-     dwords += 2;
+     dwords += 6;
    if (rrb)
-     dwords += 2;
+     dwords += 6;
    BEGIN_BATCH_NO_AUTOSTATE(dwords);
 
    /* In the CS case we need to split this up */
@@ -453,9 +454,7 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
    if (rrb) {
      OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0));
      OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
-   }
 
-   if (rrb) {
      OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
      OUT_BATCH(cbpitch);
    }
@@ -558,7 +557,7 @@ static void tex_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
 
    if (hastexture) {
      OUT_BATCH(CP_PACKET0(RADEON_PP_TXOFFSET_0 + (24 * i), 0));
-     if (t && t->mt && !t->image_override) {
+     if (t->mt && !t->image_override) {
         if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) {
             lvl = &t->mt->levels[0];
            OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset,
@@ -593,22 +592,16 @@ void radeonInitState( r100ContextPtr rmesa )
    switch ( ctx->Visual.depthBits ) {
    case 16:
       rmesa->radeon.state.depth.clear = 0x0000ffff;
-      rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffff;
       rmesa->radeon.state.stencil.clear = 0x00000000;
       break;
    case 24:
       rmesa->radeon.state.depth.clear = 0x00ffffff;
-      rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffffff;
       rmesa->radeon.state.stencil.clear = 0xffff0000;
       break;
    default:
       break;
    }
 
-   /* Only have hw stencil when depth buffer is 24 bits deep */
-   rmesa->radeon.state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 &&
-                                    ctx->Visual.depthBits == 24 );
-
    rmesa->radeon.Fallback = 0;