i915: Remove most of the code under gen >= 4 checks.

[mesa.git] / src / mesa / drivers / dri / radeon / radeon_state_init.c

diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c
index 48929faaa8b6551b12c7a340d0dfb533d62360db..8c88dd01831deb4d85b0eb44a8d546519c09df4e 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_state_init.c
+++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c
@@ -202,10 +202,10 @@ static int check_##NM( struct gl_context *ctx, struct radeon_state_atom *atom )
 CHECK( always, GL_TRUE, 0 )
 CHECK( always_add2, GL_TRUE, 2 )
 CHECK( always_add4, GL_TRUE, 4 )
-CHECK( tex0_mm, ctx->Texture.Unit[0]._ReallyEnabled, 3 )
-CHECK( tex1_mm, ctx->Texture.Unit[1]._ReallyEnabled, 3 )
+CHECK( tex0_mm, GL_TRUE, 3 )
+CHECK( tex1_mm, GL_TRUE, 3 )
 /* need this for the cubic_map on disabled unit 2 bug, maybe r100 only? */
-CHECK( tex2_mm, ctx->Texture._EnabledUnits, 3 )
+CHECK( tex2_mm, GL_TRUE, 3 )
 CHECK( cube0_mm, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_CUBE_BIT), 2 + 4*5 - CUBE_STATE_SIZE )
 CHECK( cube1_mm, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_CUBE_BIT), 2 + 4*5 - CUBE_STATE_SIZE )
 CHECK( cube2_mm, (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_CUBE_BIT), 2 + 4*5 - CUBE_STATE_SIZE )
@@ -334,7 +334,7 @@ static void ctx_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom)
    atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
    if (rrb->cpp == 4)
        atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
-   else switch (rrb->base.Format) {
+   else switch (rrb->base.Base.Format) {
    case MESA_FORMAT_RGB565:
        atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
        break;
@@ -351,6 +351,8 @@ static void ctx_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom)
    cbpitch = (rrb->pitch / rrb->cpp);
    if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
        cbpitch |= R200_COLOR_TILE_ENABLE;
+   if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE)
+       cbpitch |= RADEON_COLOR_MICROTILE_ENABLE;
 
    drb = radeon_get_depthbuffer(&r100->radeon);
    if (drb) {
@@ -402,8 +404,8 @@ static void ctx_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom)
    OUT_BATCH(0);
    OUT_BATCH(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
    if (rrb) {
-       OUT_BATCH(((rrb->base.Width - 1) << RADEON_RE_WIDTH_SHIFT) |
-                 ((rrb->base.Height - 1) << RADEON_RE_HEIGHT_SHIFT));
+       OUT_BATCH(((rrb->base.Base.Width - 1) << RADEON_RE_WIDTH_SHIFT) |
+                 ((rrb->base.Base.Height - 1) << RADEON_RE_HEIGHT_SHIFT));
    } else {
        OUT_BATCH(0);
    }
@@ -501,24 +503,9 @@ static void tex_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom)
  */
 void radeonInitState( r100ContextPtr rmesa )
 {
-   struct gl_context *ctx = rmesa->radeon.glCtx;
+   struct gl_context *ctx = &rmesa->radeon.glCtx;
    GLuint i;
 
-   rmesa->radeon.state.color.clear = 0x00000000;
-
-   switch ( ctx->Visual.depthBits ) {
-   case 16:
-      rmesa->radeon.state.depth.clear = 0x0000ffff;
-      rmesa->radeon.state.stencil.clear = 0x00000000;
-      break;
-   case 24:
-      rmesa->radeon.state.depth.clear = 0x00ffffff;
-      rmesa->radeon.state.stencil.clear = 0xffff0000;
-      break;
-   default:
-      break;
-   }
-
    rmesa->radeon.Fallback = 0;
 
 
@@ -527,8 +514,8 @@ void radeonInitState( r100ContextPtr rmesa )
 #define ALLOC_STATE_IDX( ATOM, CHK, SZ, NM, FLAG, IDX )                \
    do {                                                                \
       rmesa->hw.ATOM.cmd_size = SZ;                            \
-      rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
-      rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
+      rmesa->hw.ATOM.cmd = (GLuint *) calloc(SZ, sizeof(int));          \
+      rmesa->hw.ATOM.lastcmd = (GLuint *) calloc(SZ, sizeof(int));      \
       rmesa->hw.ATOM.name = NM;                                                \
       rmesa->hw.ATOM.is_tcl = FLAG;                                    \
       rmesa->hw.ATOM.check = check_##CHK;                              \