/* =============================================================
* State initialization
*/
-
-void radeonPrintDirty( r100ContextPtr rmesa, const char *msg )
-{
- struct radeon_state_atom *l;
-
- fprintf(stderr, msg);
- fprintf(stderr, ": ");
-
- foreach(l, &rmesa->radeon.hw.atomlist) {
- if (l->dirty || rmesa->radeon.hw.all_dirty)
- fprintf(stderr, "%s, ", l->name);
- }
-
- fprintf(stderr, "\n");
-}
-
static int cmdpkt( r100ContextPtr rmesa, int id )
{
drm_radeon_cmd_header_t h;
// }
END_BATCH();
+ BEGIN_BATCH_NO_AUTOSTATE(4);
+ OUT_BATCH(CP_PACKET0(RADEON_RE_TOP_LEFT, 0));
+ OUT_BATCH(0);
+ OUT_BATCH(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
+ if (rrb) {
+ OUT_BATCH(((rrb->width - 1) << RADEON_RE_WIDTH_SHIFT) |
+ ((rrb->height - 1) << RADEON_RE_HEIGHT_SHIFT));
+ } else {
+ OUT_BATCH(0);
+ }
+ END_BATCH();
}
static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom)
switch ( ctx->Visual.depthBits ) {
case 16:
rmesa->radeon.state.depth.clear = 0x0000ffff;
- rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffff;
rmesa->radeon.state.stencil.clear = 0x00000000;
break;
case 24:
rmesa->radeon.state.depth.clear = 0x00ffffff;
- rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffffff;
rmesa->radeon.state.stencil.clear = 0xffff0000;
break;
default:
break;
}
- /* Only have hw stencil when depth buffer is 24 bits deep */
- rmesa->radeon.state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 &&
- ctx->Visual.depthBits == 24 );
-
rmesa->radeon.Fallback = 0;