#include "main/macros.h"
#include "main/simple_list.h"
+#include "math/m_xform.h"
+
#include "swrast_setup/swrast_setup.h"
-#include "math/m_translate.h"
+
#include "tnl/tnl.h"
#include "tnl/t_context.h"
#include "tnl/t_pipeline.h"
#include "radeon_state.h"
#include "radeon_swtcl.h"
#include "radeon_tcl.h"
+#include "radeon_debug.h"
/* R100: xyzw, c0, c1/fog, stq[0..2] = 4+1+1+3*3 = 15 right? */
{ RADEON_CP_VC_FRMT_ST2, RADEON_CP_VC_FRMT_ST2 | RADEON_CP_VC_FRMT_Q2 },
};
-static void radeonSetVertexFormat( GLcontext *ctx )
+static void radeonSetVertexFormat( struct gl_context *ctx )
{
r100ContextPtr rmesa = R100_CONTEXT( ctx );
TNLcontext *tnl = TNL_CONTEXT(ctx);
struct vertex_buffer *VB = &tnl->vb;
- DECLARE_RENDERINPUTS(index_bitset);
+ GLbitfield64 index_bitset = tnl->render_inputs_bitset;
int fmt_0 = 0;
int offset = 0;
- RENDERINPUTS_COPY( index_bitset, tnl->render_inputs_bitset );
-
/* Important:
*/
if ( VB->NdcPtr != NULL ) {
* build up a hardware vertex.
*/
if ( !rmesa->swtcl.needproj ||
- RENDERINPUTS_TEST_RANGE( index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) { /* for projtex */
+ (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX))) {
+ /* for projtex */
EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F,
RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z | RADEON_CP_VC_FRMT_W0 );
offset = 4;
offset += 1;
rmesa->swtcl.specoffset = 0;
- if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 ) ||
- RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
+ if (index_bitset &
+ (BITFIELD64_BIT(_TNL_ATTRIB_COLOR1) | BITFIELD64_BIT(_TNL_ATTRIB_FOG))) {
#if MESA_LITTLE_ENDIAN
- if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 )) {
+ if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_COLOR1)) {
rmesa->swtcl.specoffset = offset;
EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_RGB,
RADEON_CP_VC_FRMT_PKSPEC );
EMIT_PAD( 3 );
}
- if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
+ if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_FOG)) {
EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
RADEON_CP_VC_FRMT_PKSPEC );
}
EMIT_PAD( 1 );
}
#else
- if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
+ if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_FOG)) {
EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
RADEON_CP_VC_FRMT_PKSPEC );
}
EMIT_PAD( 1 );
}
- if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 )) {
+ if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_COLOR1)) {
rmesa->swtcl.specoffset = offset;
EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR,
RADEON_CP_VC_FRMT_PKSPEC );
#endif
}
- if (RENDERINPUTS_TEST_RANGE( index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) {
+ if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) {
int i;
for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
- if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_TEX(i) )) {
- GLuint sz = VB->TexCoordPtr[i]->size;
+ if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_TEX(i))) {
+ GLuint sz = VB->AttribPtr[_TNL_ATTRIB_TEX0 + i]->size;
switch (sz) {
case 1:
radeon_cp_vc_frmts[i][0] );
break;
case 3:
+ if (ctx->Texture.Unit[i]._ReallyEnabled & (TEXTURE_CUBE_BIT) ) {
+ EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F,
+ radeon_cp_vc_frmts[i][1] );
+ } else {
+ EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_2F,
+ radeon_cp_vc_frmts[i][0] );
+ }
+ break;
case 4:
if (ctx->Texture.Unit[i]._ReallyEnabled & (TEXTURE_CUBE_BIT) ) {
EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F,
}
}
- if (!RENDERINPUTS_EQUAL( rmesa->radeon.tnl_index_bitset, index_bitset ) ||
- fmt_0 != rmesa->swtcl.vertex_format) {
+ if (rmesa->radeon.tnl_index_bitset != index_bitset ||
+ fmt_0 != rmesa->swtcl.vertex_format) {
RADEON_NEWPRIM(rmesa);
rmesa->swtcl.vertex_format = fmt_0;
rmesa->radeon.swtcl.vertex_size =
rmesa->radeon.swtcl.vertex_attr_count,
NULL, 0 );
rmesa->radeon.swtcl.vertex_size /= 4;
- RENDERINPUTS_COPY( rmesa->radeon.tnl_index_bitset, index_bitset );
- if (RADEON_DEBUG & DEBUG_VERTS)
- fprintf( stderr, "%s: vertex_size= %d floats\n",
- __FUNCTION__, rmesa->radeon.swtcl.vertex_size);
+ rmesa->radeon.tnl_index_bitset = index_bitset;
+ radeon_print(RADEON_SWRENDER, RADEON_VERBOSE,
+ "%s: vertex_size= %d floats\n", __FUNCTION__, rmesa->radeon.swtcl.vertex_size);
}
}
+static void radeon_predict_emit_size( r100ContextPtr rmesa )
+{
-static void radeonRenderStart( GLcontext *ctx )
+ if (!rmesa->radeon.swtcl.emit_prediction) {
+ const int state_size = radeonCountStateEmitSize( &rmesa->radeon );
+ const int scissor_size = 8;
+ const int prims_size = 8;
+ const int vertex_size = 7;
+
+ if (rcommonEnsureCmdBufSpace(&rmesa->radeon,
+ state_size +
+ (scissor_size + prims_size + vertex_size),
+ __FUNCTION__))
+ rmesa->radeon.swtcl.emit_prediction = radeonCountStateEmitSize( &rmesa->radeon );
+ else
+ rmesa->radeon.swtcl.emit_prediction = state_size;
+ rmesa->radeon.swtcl.emit_prediction += scissor_size + prims_size + vertex_size
+ + rmesa->radeon.cmdbuf.cs->cdw;
+ }
+}
+
+static void radeonRenderStart( struct gl_context *ctx )
{
- r100ContextPtr rmesa = R100_CONTEXT( ctx );
+ r100ContextPtr rmesa = R100_CONTEXT( ctx );
- radeonSetVertexFormat( ctx );
-
- if (rmesa->radeon.dma.flush != 0 &&
- rmesa->radeon.dma.flush != rcommon_flush_last_swtcl_prim)
- rmesa->radeon.dma.flush( ctx );
+ radeonSetVertexFormat( ctx );
+
+ if (rmesa->radeon.dma.flush != 0 &&
+ rmesa->radeon.dma.flush != rcommon_flush_last_swtcl_prim)
+ rmesa->radeon.dma.flush( ctx );
}
* determine in advance whether or not the hardware can / should do the
* projection divide or Mesa should do it.
*/
-void radeonChooseVertexState( GLcontext *ctx )
+void radeonChooseVertexState( struct gl_context *ctx )
{
r100ContextPtr rmesa = R100_CONTEXT( ctx );
TNLcontext *tnl = TNL_CONTEXT(ctx);
GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT];
+ GLboolean unfilled = (ctx->Polygon.FrontMode != GL_FILL ||
+ ctx->Polygon.BackMode != GL_FILL);
+ GLboolean twosided = ctx->Light.Enabled && ctx->Light.Model.TwoSide;
se_coord_fmt &= ~(RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
RADEON_VTX_Z_PRE_MULT_1_OVER_W0 |
* bigger one.
*/
- if ((!RENDERINPUTS_TEST_RANGE( tnl->render_inputs_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX ) &&
- !RENDERINPUTS_TEST( tnl->render_inputs_bitset, _TNL_ATTRIB_COLOR1 ))
- || (ctx->_TriangleCaps & (DD_TRI_LIGHT_TWOSIDE|DD_TRI_UNFILLED))) {
+ if ((0 == (tnl->render_inputs_bitset &
+ (BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)
+ | BITFIELD64_BIT(_TNL_ATTRIB_COLOR1))))
+ || twosided
+ || unfilled) {
rmesa->swtcl.needproj = GL_TRUE;
se_coord_fmt |= (RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
RADEON_VTX_Z_PRE_MULT_1_OVER_W0);
}
}
-void r100_swtcl_flush(GLcontext *ctx, uint32_t current_offset)
+void r100_swtcl_flush(struct gl_context *ctx, uint32_t current_offset)
{
r100ContextPtr rmesa = R100_CONTEXT(ctx);
- rcommonEnsureCmdBufSpace(&rmesa->radeon,
- radeonCountStateEmitSize( &rmesa->radeon ) + (12*sizeof(int)),
- __FUNCTION__);
radeonEmitState(&rmesa->radeon);
radeonEmitVertexAOS( rmesa,
rmesa->radeon.swtcl.vertex_size,
- first_elem(&rmesa->radeon.dma.reserved)->bo,
+ rmesa->radeon.swtcl.bo,
current_offset);
rmesa->swtcl.vertex_format,
rmesa->radeon.swtcl.hw_primitive,
rmesa->radeon.swtcl.numverts);
+ if ( rmesa->radeon.swtcl.emit_prediction < rmesa->radeon.cmdbuf.cs->cdw )
+ WARN_ONCE("Rendering was %d commands larger than predicted size."
+ " We might overflow command buffer.\n",
+ rmesa->radeon.cmdbuf.cs->cdw - rmesa->radeon.swtcl.emit_prediction );
+
+
+ rmesa->radeon.swtcl.emit_prediction = 0;
}
// assert(rmesa->radeon.dma.current.ptr == rmesa->radeon.dma.current.start);
}
+static void* radeon_alloc_verts( r100ContextPtr rmesa , GLuint nr, GLuint size )
+{
+ void *rv;
+ do {
+ radeon_predict_emit_size( rmesa );
+ rv = rcommonAllocDmaLowVerts( &rmesa->radeon, nr, size );
+ } while (!rv);
+ return rv;
+}
+
#define LOCAL_VARS r100ContextPtr rmesa = R100_CONTEXT(ctx)
#define INIT( prim ) radeonDmaPrimitive( rmesa, prim )
#define FLUSH() RADEON_NEWPRIM( rmesa )
// (((int)rmesa->radeon.dma.current.end - (int)rmesa->radeon.dma.current.ptr) / (rmesa->radeon.swtcl.vertex_size*4))
#define GET_SUBSEQUENT_VB_MAX_VERTS() \
((RADEON_BUFFER_SIZE) / (rmesa->radeon.swtcl.vertex_size*4))
-#define ALLOC_VERTS( nr ) \
- rcommonAllocDmaLowVerts( &rmesa->radeon, nr, rmesa->radeon.swtcl.vertex_size * 4 )
+#define ALLOC_VERTS( nr ) radeon_alloc_verts( rmesa, nr, rmesa->radeon.swtcl.vertex_size * 4 )
#define EMIT_VERTS( ctx, j, nr, buf ) \
_tnl_emit_vertices_to_buffer(ctx, j, (j)+(nr), buf)
/**********************************************************************/
-static GLboolean radeon_run_render( GLcontext *ctx,
+static GLboolean radeon_run_render( struct gl_context *ctx,
struct tnl_pipeline_stage *stage )
{
r100ContextPtr rmesa = R100_CONTEXT(ctx);
!radeon_dma_validate_render( ctx, VB ))
return GL_TRUE;
+ radeon_prepare_render(&rmesa->radeon);
+ if (rmesa->radeon.NewGLState)
+ radeonValidateState( ctx );
+
tnl->Driver.Render.Start( ctx );
for (i = 0 ; i < VB->PrimitiveCount ; i++)
if (!length)
continue;
- if (RADEON_DEBUG & DEBUG_PRIMS)
- fprintf(stderr, "radeon_render.c: prim %s %d..%d\n",
+ radeon_print(RADEON_SWRENDER, RADEON_NORMAL,
+ "radeon_render.c: prim %s %d..%d\n",
_mesa_lookup_enum_by_nr(prim & PRIM_MODE_MASK),
start, start+length);
RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
};
-static void radeonRasterPrimitive( GLcontext *ctx, GLuint hwprim );
-static void radeonRenderPrimitive( GLcontext *ctx, GLenum prim );
-static void radeonResetLineStipple( GLcontext *ctx );
+static void radeonRasterPrimitive( struct gl_context *ctx, GLuint hwprim );
+static void radeonRenderPrimitive( struct gl_context *ctx, GLenum prim );
+static void radeonResetLineStipple( struct gl_context *ctx );
/***********************************************************************
#undef ALLOC_VERTS
#define CTX_ARG r100ContextPtr rmesa
#define GET_VERTEX_DWORDS() rmesa->radeon.swtcl.vertex_size
-#define ALLOC_VERTS( n, size ) rcommonAllocDmaLowVerts( &rmesa->radeon, n, (size) * 4 )
+#define ALLOC_VERTS( n, size ) radeon_alloc_verts( rmesa, n, (size) * 4 )
#undef LOCAL_VARS
#define LOCAL_VARS \
r100ContextPtr rmesa = R100_CONTEXT(ctx); \
#define DO_POINTS 1
#define DO_FULL_QUAD 1
-#define HAVE_RGBA 1
#define HAVE_SPEC 1
#define HAVE_BACK_COLORS 0
#define HAVE_HW_FLATSHADE 1
/* Choose render functions */
/**********************************************************************/
-void radeonChooseRenderState( GLcontext *ctx )
+void radeonChooseRenderState( struct gl_context *ctx )
{
TNLcontext *tnl = TNL_CONTEXT(ctx);
r100ContextPtr rmesa = R100_CONTEXT(ctx);
GLuint index = 0;
- GLuint flags = ctx->_TriangleCaps;
+ GLboolean unfilled = (ctx->Polygon.FrontMode != GL_FILL ||
+ ctx->Polygon.BackMode != GL_FILL);
+ GLboolean twosided = ctx->Light.Enabled && ctx->Light.Model.TwoSide;
if (!rmesa->radeon.TclFallback || rmesa->radeon.Fallback)
return;
- if (flags & DD_TRI_LIGHT_TWOSIDE) index |= RADEON_TWOSIDE_BIT;
- if (flags & DD_TRI_UNFILLED) index |= RADEON_UNFILLED_BIT;
+ if (twosided)
+ index |= RADEON_TWOSIDE_BIT;
+ if (unfilled)
+ index |= RADEON_UNFILLED_BIT;
if (index != rmesa->radeon.swtcl.RenderIndex) {
tnl->Driver.Render.Points = rast_tab[index].points;
/**********************************************************************/
-static void radeonRasterPrimitive( GLcontext *ctx, GLuint hwprim )
+static void radeonRasterPrimitive( struct gl_context *ctx, GLuint hwprim )
{
r100ContextPtr rmesa = R100_CONTEXT(ctx);
}
}
-static void radeonRenderPrimitive( GLcontext *ctx, GLenum prim )
+static void radeonRenderPrimitive( struct gl_context *ctx, GLenum prim )
{
r100ContextPtr rmesa = R100_CONTEXT(ctx);
+ GLboolean unfilled = (ctx->Polygon.FrontMode != GL_FILL ||
+ ctx->Polygon.BackMode != GL_FILL);
+
rmesa->radeon.swtcl.render_primitive = prim;
- if (prim < GL_TRIANGLES || !(ctx->_TriangleCaps & DD_TRI_UNFILLED))
+ if (prim < GL_TRIANGLES || !unfilled)
radeonRasterPrimitive( ctx, reduced_hw_prim[prim] );
}
-static void radeonRenderFinish( GLcontext *ctx )
+static void radeonRenderFinish( struct gl_context *ctx )
{
}
-static void radeonResetLineStipple( GLcontext *ctx )
+static void radeonResetLineStipple( struct gl_context *ctx )
{
r100ContextPtr rmesa = R100_CONTEXT(ctx);
RADEON_STATECHANGE( rmesa, lin );
}
-void radeonFallback( GLcontext *ctx, GLuint bit, GLboolean mode )
+void radeonFallback( struct gl_context *ctx, GLuint bit, GLboolean mode )
{
r100ContextPtr rmesa = R100_CONTEXT(ctx);
TNLcontext *tnl = TNL_CONTEXT(ctx);
TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_TRUE );
_swsetup_Wakeup( ctx );
rmesa->radeon.swtcl.RenderIndex = ~0;
- if (RADEON_DEBUG & DEBUG_FALLBACKS) {
+ if (RADEON_DEBUG & RADEON_FALLBACKS) {
fprintf(stderr, "Radeon begin rasterization fallback: 0x%x %s\n",
bit, getFallbackString(bit));
}
*/
_tnl_invalidate_vertex_state( ctx, ~0 );
_tnl_invalidate_vertices( ctx, ~0 );
- RENDERINPUTS_ZERO( rmesa->radeon.tnl_index_bitset );
+ rmesa->radeon.tnl_index_bitset = 0;
radeonChooseVertexState( ctx );
radeonChooseRenderState( ctx );
}
- if (RADEON_DEBUG & DEBUG_FALLBACKS) {
+ if (RADEON_DEBUG & RADEON_FALLBACKS) {
fprintf(stderr, "Radeon end rasterization fallback: 0x%x %s\n",
bit, getFallbackString(bit));
}
/* Initialization. */
/**********************************************************************/
-void radeonInitSwtcl( GLcontext *ctx )
+void radeonInitSwtcl( struct gl_context *ctx )
{
TNLcontext *tnl = TNL_CONTEXT(ctx);
r100ContextPtr rmesa = R100_CONTEXT(ctx);
init_rast_tab();
firsttime = 0;
}
+ rmesa->radeon.swtcl.emit_prediction = 0;
tnl->Driver.Render.Start = radeonRenderStart;
tnl->Driver.Render.Finish = radeonRenderFinish;
projects / mesa.git / blobdiff