Close some races with locking on R100 and R200 which could manifest as rendering

[mesa.git] / src / mesa / drivers / dri / radeon / radeon_tcl.c

diff --git a/src/mesa/drivers/dri/radeon/radeon_tcl.c b/src/mesa/drivers/dri/radeon/radeon_tcl.c
index 651194a8047763d93f84fc297477350aec5df0a1..6e294d2395c9fd3344fa079b057accc2b3b80ada 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_tcl.c
+++ b/src/mesa/drivers/dri/radeon/radeon_tcl.c
@@ -149,6 +149,9 @@ static GLushort *radeonAllocElts( radeonContextPtr rmesa, GLuint nr )
    if (rmesa->dma.flush)
       rmesa->dma.flush( rmesa );
 
+   radeonEnsureCmdBufSpace(rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) +
+                          rmesa->hw.max_state_size + ELTS_BUFSZ(nr));
+
    radeonEmitAOS( rmesa,
                rmesa->tcl.aos_components,
                rmesa->tcl.nr_aos_components, 0 );
@@ -175,6 +178,9 @@ static void EMIT_PRIM( GLcontext *ctx,
    radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
    radeonTclPrimitive( ctx, prim, hwprim );
    
+   radeonEnsureCmdBufSpace( rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) +
+                           rmesa->hw.max_state_size + VBUF_BUFSZ );
+
    radeonEmitAOS( rmesa,
                  rmesa->tcl.aos_components,
                  rmesa->tcl.nr_aos_components,
@@ -277,12 +283,12 @@ void radeonTclPrimitive( GLcontext *ctx,
 /* TCL render.
  */
 static GLboolean radeon_run_tcl_render( GLcontext *ctx,
-                                       struct gl_pipeline_stage *stage )
+                                       struct tnl_pipeline_stage *stage )
 {
    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
    TNLcontext *tnl = TNL_CONTEXT(ctx);
    struct vertex_buffer *VB = &tnl->vb;
-   GLuint i,flags = 0,length;
+   GLuint i;
 
    /* TODO: separate this from the swtnl pipeline 
     */
@@ -297,24 +303,19 @@ static GLboolean radeon_run_tcl_render( GLcontext *ctx,
 
    rmesa->tcl.Elts = VB->Elts;
 
-   for (i = VB->FirstPrimitive ; !(flags & PRIM_LAST) ; i += length)
+   for (i = 0 ; i < VB->PrimitiveCount ; i++)
    {
-      flags = VB->Primitive[i];
-      length = VB->PrimitiveLength[i];
-
-      if (RADEON_DEBUG & DEBUG_PRIMS)
-        fprintf(stderr, "%s: prim %s %d..%d\n", 
-                __FUNCTION__,
-                _mesa_lookup_enum_by_nr(flags & PRIM_MODE_MASK), 
-                i, i+length);
+      GLuint prim = VB->Primitive[i].mode;
+      GLuint start = VB->Primitive[i].start;
+      GLuint length = VB->Primitive[i].count;
 
       if (!length)
         continue;
 
       if (rmesa->tcl.Elts)
-        radeonEmitEltPrimitive( ctx, i, i+length, flags );
+        radeonEmitEltPrimitive( ctx, start, start+length, prim );
       else
-        radeonEmitPrimitive( ctx, i, i+length, flags );
+        radeonEmitPrimitive( ctx, start, start+length, prim );
    }
 
    return GL_FALSE;            /* finished the pipe */
@@ -323,7 +324,7 @@ static GLboolean radeon_run_tcl_render( GLcontext *ctx,
 
 
 static void radeon_check_tcl_render( GLcontext *ctx,
-                                    struct gl_pipeline_stage *stage )
+                                    struct tnl_pipeline_stage *stage )
 {
    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
    GLuint inputs = VERT_BIT_POS;
@@ -374,13 +375,13 @@ static void radeon_check_tcl_render( GLcontext *ctx,
 }
 
 static void radeon_init_tcl_render( GLcontext *ctx,
-                                   struct gl_pipeline_stage *stage )
+                                   struct tnl_pipeline_stage *stage )
 {
    stage->check = radeon_check_tcl_render;
    stage->check( ctx, stage );
 }
 
-static void dtr( struct gl_pipeline_stage *stage )
+static void dtr( struct tnl_pipeline_stage *stage )
 {
    (void)stage;
 }
@@ -388,7 +389,7 @@ static void dtr( struct gl_pipeline_stage *stage )
 
 /* Initial state for tcl stage.  
  */
-const struct gl_pipeline_stage _radeon_tcl_stage =
+const struct tnl_pipeline_stage _radeon_tcl_stage =
 {
    "radeon render",
    (_DD_NEW_SEPARATE_SPECULAR |