Merge branch 'mesa_7_5_branch'

[mesa.git] / src / mesa / shader / prog_instruction.c

diff --git a/src/mesa/shader/prog_instruction.c b/src/mesa/shader/prog_instruction.c
index 1033496d9789554e3cc3a8011a2ad35f4ced9480..44c961927a382c6532aed5c89443da2d2ae3c732 100644 (file)
--- a/src/mesa/shader/prog_instruction.c
+++ b/src/mesa/shader/prog_instruction.c
@@ -1,8 +1,9 @@
 /*
  * Mesa 3-D graphics library
- * Version:  6.5.3
+ * Version:  7.3
  *
- * Copyright (C) 1999-2005  Brian Paul   All Rights Reserved.
+ * Copyright (C) 1999-2008  Brian Paul   All Rights Reserved.
+ * Copyright (C) 1999-2009  VMware, Inc.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -154,9 +155,10 @@ static const struct instruction_info InstInfo[MAX_OPCODE] = {
    { OPCODE_NOP,    "NOP",     0, 0 },
    { OPCODE_ABS,    "ABS",     1, 1 },
    { OPCODE_ADD,    "ADD",     2, 1 },
+   { OPCODE_AND,    "AND",     2, 1 },
    { OPCODE_ARA,    "ARA",     1, 1 },
    { OPCODE_ARL,    "ARL",     1, 1 },
-   { OPCODE_ARL_NV, "ARL",     1, 1 },
+   { OPCODE_ARL_NV, "ARL_NV",  1, 1 },
    { OPCODE_ARR,    "ARL",     1, 1 },
    { OPCODE_BGNLOOP,"BGNLOOP", 0, 0 },
    { OPCODE_BGNSUB, "BGNSUB",  0, 0 },
@@ -168,6 +170,8 @@ static const struct instruction_info InstInfo[MAX_OPCODE] = {
    { OPCODE_COS,    "COS",     1, 1 },
    { OPCODE_DDX,    "DDX",     1, 1 },
    { OPCODE_DDY,    "DDY",     1, 1 },
+   { OPCODE_DP2,    "DP2",     2, 1 },
+   { OPCODE_DP2A,   "DP2A",    3, 1 },
    { OPCODE_DP3,    "DP3",     2, 1 },
    { OPCODE_DP4,    "DP4",     2, 1 },
    { OPCODE_DPH,    "DPH",     2, 1 },
@@ -182,9 +186,8 @@ static const struct instruction_info InstInfo[MAX_OPCODE] = {
    { OPCODE_FLR,    "FLR",     1, 1 },
    { OPCODE_FRC,    "FRC",     1, 1 },
    { OPCODE_IF,     "IF",      1, 0 },
-   { OPCODE_INT,    "INT",     1, 1 },
    { OPCODE_KIL,    "KIL",     1, 0 },
-   { OPCODE_KIL_NV, "KIL",     0, 0 },
+   { OPCODE_KIL_NV, "KIL_NV",  0, 0 },
    { OPCODE_LG2,    "LG2",     1, 1 },
    { OPCODE_LIT,    "LIT",     1, 1 },
    { OPCODE_LOG,    "LOG",     1, 1 },
@@ -198,6 +201,10 @@ static const struct instruction_info InstInfo[MAX_OPCODE] = {
    { OPCODE_NOISE2, "NOISE2",  1, 1 },
    { OPCODE_NOISE3, "NOISE3",  1, 1 },
    { OPCODE_NOISE4, "NOISE4",  1, 1 },
+   { OPCODE_NOT,    "NOT",     1, 1 },
+   { OPCODE_NRM3,   "NRM3",    1, 1 },
+   { OPCODE_NRM4,   "NRM4",    1, 1 },
+   { OPCODE_OR,     "OR",      2, 1 },
    { OPCODE_PK2H,   "PK2H",    1, 1 },
    { OPCODE_PK2US,  "PK2US",   1, 1 },
    { OPCODE_PK4B,   "PK4B",    1, 1 },
@@ -229,12 +236,14 @@ static const struct instruction_info InstInfo[MAX_OPCODE] = {
    { OPCODE_TXD,    "TXD",     3, 1 },
    { OPCODE_TXL,    "TXL",     1, 1 },
    { OPCODE_TXP,    "TXP",     1, 1 },
-   { OPCODE_TXP_NV, "TXP",     1, 1 },
+   { OPCODE_TXP_NV, "TXP_NV",  1, 1 },
+   { OPCODE_TRUNC,  "TRUNC",   1, 1 },
    { OPCODE_UP2H,   "UP2H",    1, 1 },
    { OPCODE_UP2US,  "UP2US",   1, 1 },
    { OPCODE_UP4B,   "UP4B",    1, 1 },
    { OPCODE_UP4UB,  "UP4UB",   1, 1 },
    { OPCODE_X2D,    "X2D",     3, 1 },
+   { OPCODE_XOR,    "XOR",     2, 1 },
    { OPCODE_XPD,    "XPD",     2, 1 }
 };
 
@@ -245,6 +254,7 @@ static const struct instruction_info InstInfo[MAX_OPCODE] = {
 GLuint
 _mesa_num_inst_src_regs(gl_inst_opcode opcode)
 {
+   ASSERT(opcode < MAX_OPCODE);
    ASSERT(opcode == InstInfo[opcode].Opcode);
    ASSERT(OPCODE_XPD == InstInfo[OPCODE_XPD].Opcode);
    return InstInfo[opcode].NumSrcRegs;
@@ -257,6 +267,7 @@ _mesa_num_inst_src_regs(gl_inst_opcode opcode)
 GLuint
 _mesa_num_inst_dst_regs(gl_inst_opcode opcode)
 {
+   ASSERT(opcode < MAX_OPCODE);
    ASSERT(opcode == InstInfo[opcode].Opcode);
    ASSERT(OPCODE_XPD == InstInfo[OPCODE_XPD].Opcode);
    return InstInfo[opcode].NumDstRegs;
@@ -274,13 +285,68 @@ _mesa_is_tex_instruction(gl_inst_opcode opcode)
 }
 
 
+/**
+ * Check if there's a potential src/dst register data dependency when
+ * using SOA execution.
+ * Example:
+ *   MOV T, T.yxwz;
+ * This would expand into:
+ *   MOV t0, t1;
+ *   MOV t1, t0;
+ *   MOV t2, t3;
+ *   MOV t3, t2;
+ * The second instruction will have the wrong value for t0 if executed as-is.
+ */
+GLboolean
+_mesa_check_soa_dependencies(const struct prog_instruction *inst)
+{
+   GLuint i, chan;
+
+   if (inst->DstReg.WriteMask == WRITEMASK_X ||
+       inst->DstReg.WriteMask == WRITEMASK_Y ||
+       inst->DstReg.WriteMask == WRITEMASK_Z ||
+       inst->DstReg.WriteMask == WRITEMASK_W ||
+       inst->DstReg.WriteMask == 0x0) {
+      /* no chance of data dependency */
+      return GL_FALSE;
+   }
+
+   /* loop over src regs */
+   for (i = 0; i < 3; i++) {
+      if (inst->SrcReg[i].File == inst->DstReg.File &&
+          inst->SrcReg[i].Index == inst->DstReg.Index) {
+         /* loop over dest channels */
+         GLuint channelsWritten = 0x0;
+         for (chan = 0; chan < 4; chan++) {
+            if (inst->DstReg.WriteMask & (1 << chan)) {
+               /* check if we're reading a channel that's been written */
+               GLuint swizzle = GET_SWZ(inst->SrcReg[i].Swizzle, chan);
+               if (swizzle <= SWIZZLE_W &&
+                   (channelsWritten & (1 << swizzle))) {
+                  return GL_TRUE;
+               }
+
+               channelsWritten |= (1 << chan);
+            }
+         }
+      }
+   }
+   return GL_FALSE;
+}
+
+
 /**
  * Return string name for given program opcode.
  */
 const char *
 _mesa_opcode_string(gl_inst_opcode opcode)
 {
-   ASSERT(opcode < MAX_OPCODE);
-   return InstInfo[opcode].Name;
+   if (opcode < MAX_OPCODE)
+      return InstInfo[opcode].Name;
+   else {
+      static char s[20];
+      _mesa_snprintf(s, sizeof(s), "OP%u", opcode);
+      return s;
+   }
 }