#include "main/uniforms.h"
#include "st_context.h"
+#include "st_glsl_types.h"
#include "st_program.h"
#include "compiler/nir/nir.h"
if ((prog->info.inputs_read & BITFIELD64_BIT(attr)) != 0) {
input_to_index[attr] = num_inputs;
num_inputs++;
- if ((prog->info.double_inputs_read & BITFIELD64_BIT(attr)) != 0) {
+ if ((prog->info.vs.double_inputs_read & BITFIELD64_BIT(attr)) != 0) {
/* add placeholder for second part of a double attribute */
num_inputs++;
}
}
static void
-st_nir_assign_var_locations(struct exec_list *var_list, unsigned *size)
+st_nir_assign_var_locations(struct exec_list *var_list, unsigned *size,
+ gl_shader_stage stage)
{
unsigned location = 0;
- unsigned assigned_locations[VARYING_SLOT_MAX];
- uint64_t processed_locs = 0;
+ unsigned assigned_locations[VARYING_SLOT_TESS_MAX];
+ uint64_t processed_locs[2] = {0};
+
+ const int base = stage == MESA_SHADER_FRAGMENT ?
+ (int) FRAG_RESULT_DATA0 : (int) VARYING_SLOT_VAR0;
nir_foreach_variable(var, var_list) {
+
+ const struct glsl_type *type = var->type;
+ if (nir_is_per_vertex_io(var, stage)) {
+ assert(glsl_type_is_array(type));
+ type = glsl_get_array_element(type);
+ }
+
+ /* Builtins don't allow component packing so we only need to worry about
+ * user defined varyings sharing the same location.
+ */
+ bool processed = false;
+ if (var->data.location >= base) {
+ unsigned glsl_location = var->data.location - base;
+ if (processed_locs[var->data.index] & ((uint64_t)1 << glsl_location))
+ processed = true;
+ else
+ processed_locs[var->data.index] |= ((uint64_t)1 << glsl_location);
+ }
+
/* Because component packing allows varyings to share the same location
* we may have already have processed this location.
*/
- if (var->data.location >= VARYING_SLOT_VAR0 &&
- processed_locs & ((uint64_t)1 << var->data.location)) {
+ if (processed) {
var->data.driver_location = assigned_locations[var->data.location];
- *size += type_size(var->type);
+ *size += type_size(type);
continue;
}
assigned_locations[var->data.location] = location;
var->data.driver_location = location;
- location += type_size(var->type);
-
- processed_locs |= ((uint64_t)1 << var->data.location);
+ location += type_size(type);
}
*size += location;
}
static void
-st_nir_assign_uniform_locations(struct gl_program *prog,
+st_nir_assign_uniform_locations(struct gl_context *ctx,
+ struct gl_program *prog,
struct gl_shader_program *shader_program,
struct exec_list *uniform_list, unsigned *size)
{
continue;
if (uniform->type->is_sampler() || uniform->type->is_image()) {
- unsigned val = 0;
- bool found = shader_program->UniformHash->get(val, uniform->name);
if (uniform->type->is_sampler())
loc = shaderidx++;
else
loc = imageidx++;
- assert(found);
- (void) found; /* silence unused var warning */
- /* this ensure that nir_lower_samplers looks at the correct
- * shader_program->UniformStorage[location]:
- */
- uniform->data.location = val;
} else if (strncmp(uniform->name, "gl_", 3) == 0) {
- const gl_state_index *const stateTokens = (gl_state_index *)uniform->state_slots[0].tokens;
+ const gl_state_index16 *const stateTokens = uniform->state_slots[0].tokens;
/* This state reference has already been setup by ir_to_mesa, but we'll
* get the same index back here.
*/
- loc = _mesa_add_state_reference(prog->Parameters, stateTokens);
+
+ unsigned comps;
+ const struct glsl_type *type = glsl_without_array(uniform->type);
+ if (glsl_type_is_struct(type)) {
+ comps = 4;
+ } else {
+ comps = glsl_get_vector_elements(type);
+ }
+
+ if (ctx->Const.PackedDriverUniformStorage) {
+ loc = _mesa_add_sized_state_reference(prog->Parameters,
+ stateTokens, comps, false);
+ } else {
+ loc = _mesa_add_state_reference(prog->Parameters, stateTokens);
+ }
} else {
loc = st_nir_lookup_parameter_index(prog->Parameters, uniform->name);
}
do {
progress = false;
+ NIR_PASS_V(nir, nir_lower_vars_to_ssa);
+ NIR_PASS_V(nir, nir_lower_alu_to_scalar);
+ NIR_PASS_V(nir, nir_lower_phis_to_scalar);
+
+ NIR_PASS_V(nir, nir_lower_64bit_pack);
NIR_PASS(progress, nir, nir_copy_prop);
NIR_PASS(progress, nir, nir_opt_remove_phis);
NIR_PASS(progress, nir, nir_opt_dce);
struct gl_shader_program *shader_program,
gl_shader_stage stage)
{
- struct pipe_screen *pscreen = st->pipe->screen;
- enum pipe_shader_type ptarget = pipe_shader_type_from_mesa(stage);
- const nir_shader_compiler_options *options;
-
- assert(pscreen->get_compiler_options); /* drivers using NIR must implement this */
-
- options = (const nir_shader_compiler_options *)
- pscreen->get_compiler_options(pscreen, PIPE_SHADER_IR_NIR, ptarget);
+ const nir_shader_compiler_options *options =
+ st->ctx->Const.ShaderCompilerOptions[prog->info.stage].NirOptions;
assert(options);
if (prog->nir)
nir_shader *nir = glsl_to_nir(shader_program, stage, options);
+ nir_variable_mode mask =
+ (nir_variable_mode) (nir_var_shader_in | nir_var_shader_out);
+ nir_remove_dead_variables(nir, mask);
+
+ if (options->lower_all_io_to_temps ||
+ nir->info.stage == MESA_SHADER_VERTEX ||
+ nir->info.stage == MESA_SHADER_GEOMETRY) {
+ NIR_PASS_V(nir, nir_lower_io_to_temporaries,
+ nir_shader_get_entrypoint(nir),
+ true, true);
+ } else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
+ NIR_PASS_V(nir, nir_lower_io_to_temporaries,
+ nir_shader_get_entrypoint(nir),
+ true, false);
+ }
+
+ NIR_PASS_V(nir, nir_lower_global_vars_to_local);
+ NIR_PASS_V(nir, nir_split_var_copies);
+ NIR_PASS_V(nir, nir_lower_var_copies);
+
st_nir_opts(nir);
return nir;
const nir_state_slot *const slots = var->state_slots;
assert(var->state_slots != NULL);
+ const struct glsl_type *type = glsl_without_array(var->type);
for (unsigned int i = 0; i < var->num_state_slots; i++) {
- _mesa_add_state_reference(prog->Parameters,
- (gl_state_index *)slots[i].tokens);
+ unsigned comps;
+ if (glsl_type_is_struct(type)) {
+ /* Builtin struct require specical handling for now we just
+ * make all members vec4. See st_nir_lower_builtin.
+ */
+ comps = 4;
+ } else {
+ comps = glsl_get_vector_elements(type);
+ }
+
+ if (st->ctx->Const.PackedDriverUniformStorage) {
+ _mesa_add_sized_state_reference(prog->Parameters,
+ slots[i].tokens,
+ comps, false);
+ } else {
+ _mesa_add_state_reference(prog->Parameters,
+ slots[i].tokens);
+ }
}
}
}
*/
_mesa_associate_uniform_storage(st->ctx, shader_program, prog, true);
- /* fragment shaders may need : */
- if (prog->info.stage == MESA_SHADER_FRAGMENT) {
- static const gl_state_index wposTransformState[STATE_LENGTH] = {
- STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM
- };
- nir_lower_wpos_ytransform_options wpos_options = { { 0 } };
- struct pipe_screen *pscreen = st->pipe->screen;
-
- memcpy(wpos_options.state_tokens, wposTransformState,
- sizeof(wpos_options.state_tokens));
- wpos_options.fs_coord_origin_upper_left =
- pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT);
- wpos_options.fs_coord_origin_lower_left =
- pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
- wpos_options.fs_coord_pixel_center_integer =
- pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
- wpos_options.fs_coord_pixel_center_half_integer =
- pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER);
-
- if (nir_lower_wpos_ytransform(nir, &wpos_options)) {
- nir_validate_shader(nir);
- _mesa_add_state_reference(prog->Parameters, wposTransformState);
- }
- }
-
- NIR_PASS_V(nir, nir_lower_system_values);
-
- nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
- prog->info = nir->info;
-
st_set_prog_affected_state_flags(prog);
NIR_PASS_V(nir, st_nir_lower_builtin);
stcp = (struct st_compute_program *)prog;
stcp->shader_program = shader_program;
stcp->tgsi.ir_type = PIPE_SHADER_IR_NIR;
- stcp->tgsi.prog = nir_shader_clone(NULL, nir);
+ stcp->tgsi.prog = nir;
break;
default:
unreachable("unknown shader stage");
set_st_program(prog, shader_program, nir);
prog->nir = nir;
+}
- NIR_PASS_V(nir, nir_lower_io_to_temporaries,
- nir_shader_get_entrypoint(nir),
- true, true);
- NIR_PASS_V(nir, nir_lower_global_vars_to_local);
- NIR_PASS_V(nir, nir_split_var_copies);
- NIR_PASS_V(nir, nir_lower_var_copies);
+static void
+st_nir_link_shaders(nir_shader **producer, nir_shader **consumer)
+{
+ nir_lower_io_arrays_to_elements(*producer, *consumer);
+
+ NIR_PASS_V(*producer, nir_remove_dead_variables, nir_var_shader_out);
+ NIR_PASS_V(*consumer, nir_remove_dead_variables, nir_var_shader_in);
+
+ if (nir_remove_unused_varyings(*producer, *consumer)) {
+ NIR_PASS_V(*producer, nir_lower_global_vars_to_local);
+ NIR_PASS_V(*consumer, nir_lower_global_vars_to_local);
+
+ /* The backend might not be able to handle indirects on
+ * temporaries so we need to lower indirects on any of the
+ * varyings we have demoted here.
+ *
+ * TODO: radeonsi shouldn't need to do this, however LLVM isn't
+ * currently smart enough to handle indirects without causing excess
+ * spilling causing the gpu to hang.
+ *
+ * See the following thread for more details of the problem:
+ * https://lists.freedesktop.org/archives/mesa-dev/2017-July/162106.html
+ */
+ nir_variable_mode indirect_mask = nir_var_local;
+
+ NIR_PASS_V(*producer, nir_lower_indirect_derefs, indirect_mask);
+ NIR_PASS_V(*consumer, nir_lower_indirect_derefs, indirect_mask);
+
+ st_nir_opts(*producer);
+ st_nir_opts(*consumer);
+ }
}
extern "C" {
{
struct st_context *st = st_context(ctx);
+ /* Determine first and last stage. */
+ unsigned first = MESA_SHADER_STAGES;
+ unsigned last = 0;
+ for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
+ if (!shader_program->_LinkedShaders[i])
+ continue;
+ if (first == MESA_SHADER_STAGES)
+ first = i;
+ last = i;
+ }
+
for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
struct gl_linked_shader *shader = shader_program->_LinkedShaders[i];
if (shader == NULL)
continue;
st_nir_get_mesa_program(ctx, shader_program, shader);
+
+ nir_variable_mode mask = (nir_variable_mode) 0;
+ if (i != first)
+ mask = (nir_variable_mode)(mask | nir_var_shader_in);
+
+ if (i != last)
+ mask = (nir_variable_mode)(mask | nir_var_shader_out);
+
+ nir_shader *nir = shader->Program->nir;
+ nir_lower_io_to_scalar_early(nir, mask);
+ st_nir_opts(nir);
+ }
+
+ /* Linking the stages in the opposite order (from fragment to vertex)
+ * ensures that inter-shader outputs written to in an earlier stage
+ * are eliminated if they are (transitively) not used in a later
+ * stage.
+ */
+ int next = last;
+ for (int i = next - 1; i >= 0; i--) {
+ struct gl_linked_shader *shader = shader_program->_LinkedShaders[i];
+ if (shader == NULL)
+ continue;
+
+ st_nir_link_shaders(&shader->Program->nir,
+ &shader_program->_LinkedShaders[next]->Program->nir);
+ next = i;
+ }
+
+ int prev = -1;
+ for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
+ struct gl_linked_shader *shader = shader_program->_LinkedShaders[i];
+ if (shader == NULL)
+ continue;
+
+ nir_shader *nir = shader->Program->nir;
+
+ /* fragment shaders may need : */
+ if (nir->info.stage == MESA_SHADER_FRAGMENT) {
+ static const gl_state_index16 wposTransformState[STATE_LENGTH] = {
+ STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM
+ };
+ nir_lower_wpos_ytransform_options wpos_options = { { 0 } };
+ struct pipe_screen *pscreen = st->pipe->screen;
+
+ memcpy(wpos_options.state_tokens, wposTransformState,
+ sizeof(wpos_options.state_tokens));
+ wpos_options.fs_coord_origin_upper_left =
+ pscreen->get_param(pscreen,
+ PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT);
+ wpos_options.fs_coord_origin_lower_left =
+ pscreen->get_param(pscreen,
+ PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
+ wpos_options.fs_coord_pixel_center_integer =
+ pscreen->get_param(pscreen,
+ PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
+ wpos_options.fs_coord_pixel_center_half_integer =
+ pscreen->get_param(pscreen,
+ PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER);
+
+ if (nir_lower_wpos_ytransform(nir, &wpos_options)) {
+ nir_validate_shader(nir);
+ _mesa_add_state_reference(shader->Program->Parameters,
+ wposTransformState);
+ }
+ }
+
+ NIR_PASS_V(nir, nir_lower_system_values);
+
+ nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
+ shader->Program->info = nir->info;
+
+ if (prev != -1) {
+ nir_compact_varyings(shader_program->_LinkedShaders[prev]->Program->nir,
+ nir, ctx->API != API_OPENGL_COMPAT);
+ }
+ prev = i;
}
for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
struct gl_shader_program *shader_program, nir_shader *nir)
{
struct pipe_screen *screen = st->pipe->screen;
+ const nir_shader_compiler_options *options =
+ st->ctx->Const.ShaderCompilerOptions[prog->info.stage].NirOptions;
NIR_PASS_V(nir, nir_split_var_copies);
NIR_PASS_V(nir, nir_lower_var_copies);
- NIR_PASS_V(nir, nir_lower_io_types);
+ if (options->lower_all_io_to_temps ||
+ nir->info.stage == MESA_SHADER_VERTEX ||
+ nir->info.stage == MESA_SHADER_GEOMETRY) {
+ NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects, false);
+ } else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
+ NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects, true);
+ }
if (nir->info.stage == MESA_SHADER_VERTEX) {
/* Needs special handling so drvloc matches the vbo state: */
sort_varyings(&nir->outputs);
st_nir_assign_var_locations(&nir->outputs,
- &nir->num_outputs);
+ &nir->num_outputs,
+ nir->info.stage);
+ st_nir_fixup_varying_slots(st, &nir->outputs);
+ } else if (nir->info.stage == MESA_SHADER_GEOMETRY ||
+ nir->info.stage == MESA_SHADER_TESS_CTRL ||
+ nir->info.stage == MESA_SHADER_TESS_EVAL) {
+ sort_varyings(&nir->inputs);
+ st_nir_assign_var_locations(&nir->inputs,
+ &nir->num_inputs,
+ nir->info.stage);
+ st_nir_fixup_varying_slots(st, &nir->inputs);
+
+ sort_varyings(&nir->outputs);
+ st_nir_assign_var_locations(&nir->outputs,
+ &nir->num_outputs,
+ nir->info.stage);
st_nir_fixup_varying_slots(st, &nir->outputs);
} else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
sort_varyings(&nir->inputs);
st_nir_assign_var_locations(&nir->inputs,
- &nir->num_inputs);
+ &nir->num_inputs,
+ nir->info.stage);
st_nir_fixup_varying_slots(st, &nir->inputs);
st_nir_assign_var_locations(&nir->outputs,
- &nir->num_outputs);
+ &nir->num_outputs,
+ nir->info.stage);
} else if (nir->info.stage == MESA_SHADER_COMPUTE) {
/* TODO? */
} else {
NIR_PASS_V(nir, nir_lower_atomics_to_ssbo,
st->ctx->Const.Program[nir->info.stage].MaxAtomicBuffers);
- st_nir_assign_uniform_locations(prog, shader_program,
+ st_nir_assign_uniform_locations(st->ctx, prog, shader_program,
&nir->uniforms, &nir->num_uniforms);
+ /* Below is a quick hack so that uniform lowering only runs on radeonsi
+ * (the only NIR backend that currently supports tess) once we enable
+ * uniform packing support we will just use
+ * ctx->Const.PackedDriverUniformStorage for this check.
+ */
+ if (screen->get_shader_param(screen, PIPE_SHADER_TESS_CTRL,
+ PIPE_SHADER_CAP_MAX_INSTRUCTIONS) > 0) {
+ NIR_PASS_V(nir, nir_lower_io, nir_var_uniform, type_size,
+ (nir_lower_io_options)0);
+ NIR_PASS_V(nir, st_nir_lower_uniforms_to_ubo);
+ }
+
if (screen->get_param(screen, PIPE_CAP_NIR_SAMPLERS_AS_DEREF))
NIR_PASS_V(nir, nir_lower_samplers_as_deref, shader_program);
else
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