switch( op ) {
case OPCODE_ARL:
return TGSI_OPCODE_ARL;
- case OPCODE_ABS:
- return TGSI_OPCODE_ABS;
case OPCODE_ADD:
return TGSI_OPCODE_ADD;
case OPCODE_CMP:
return TGSI_OPCODE_SIN;
case OPCODE_SLT:
return TGSI_OPCODE_SLT;
- case OPCODE_SUB:
- return TGSI_OPCODE_SUB;
case OPCODE_TEX:
return TGSI_OPCODE_TEX;
case OPCODE_TXB:
ureg_RSQ( ureg, dst[0], ureg_abs(src[0]) );
break;
+ case OPCODE_ABS:
+ ureg_MOV(ureg, dst[0], ureg_abs(src[0]));
+ break;
+
+ case OPCODE_SUB:
+ ureg_ADD(ureg, dst[0], src[0], ureg_negate(src[1]));
+ break;
+
default:
ureg_insn( ureg,
translate_opcode( inst->Opcode ),
/* Declare address register.
*/
- if (program->NumAddressRegs > 0) {
- debug_assert( program->NumAddressRegs == 1 );
+ if (program->arb.NumAddressRegs > 0) {
+ debug_assert( program->arb.NumAddressRegs == 1 );
t->address[0] = ureg_DECL_address( ureg );
}
}
}
- if (program->IndirectRegisterFiles & (1 << PROGRAM_TEMPORARY)) {
+ if (program->arb.IndirectRegisterFiles & (1 << PROGRAM_TEMPORARY)) {
/* If temps are accessed with indirect addressing, declare temporaries
* in sequential order. Else, we declare them on demand elsewhere.
*/
- for (i = 0; i < program->NumTemporaries; i++) {
+ for (i = 0; i < program->arb.NumTemporaries; i++) {
/* XXX use TGSI_FILE_TEMPORARY_ARRAY when it's supported by ureg */
t->temps[i] = ureg_DECL_temporary( t->ureg );
}
* array.
*/
case PROGRAM_CONSTANT:
- if (program->IndirectRegisterFiles & PROGRAM_ANY_CONST)
+ if (program->arb.IndirectRegisterFiles & PROGRAM_ANY_CONST)
t->constants[i] = ureg_DECL_constant( ureg, i );
else
t->constants[i] =
/* Emit each instruction in turn:
*/
- for (i = 0; i < program->NumInstructions; i++)
- compile_instruction(ctx, t, &program->Instructions[i]);
+ for (i = 0; i < program->arb.NumInstructions; i++)
+ compile_instruction(ctx, t, &program->arb.Instructions[i]);
out:
free(t->constants);