#include "bifrost.h"
#include "compiler/nir/nir.h"
+#include "panfrost/util/pan_ir.h"
/* Bifrost opcodes are tricky -- the same op may exist on both FMA and
* ADD with two completely different opcodes, and opcodes can be varying
BI_DISCARD,
BI_FMA,
BI_FREXP,
+ BI_ISUB,
BI_LOAD,
+ BI_LOAD_UNIFORM,
BI_LOAD_ATTR,
BI_LOAD_VAR,
BI_LOAD_VAR_ADDRESS,
BI_STORE,
BI_STORE_VAR,
BI_SPECIAL, /* _FAST, _TABLE on supported GPUs */
+ BI_SWIZZLE,
BI_TEX,
BI_ROUND,
BI_NUM_CLASSES
/* Most ALU ops can do either, actually */
#define BI_SCHED_ALL (BI_SCHED_FMA | BI_SCHED_ADD)
-/* It can't get any worse than csel4... can it? */
-#define BIR_SRC_COUNT 4
+/* Along with setting BI_SCHED_ADD, eats up the entire cycle, so FMA must be
+ * nopped out. Used for _FAST operations. */
+#define BI_SCHED_SLOW (1 << 5)
-/* Class-specific data for BI_LD_ATTR, BI_LD_VAR_ADDR */
-struct bi_load {
- /* Note: no indirects here */
- unsigned location;
+/* Swizzling allowed for the 8/16-bit source */
+#define BI_SWIZZLABLE (1 << 6)
- /* Only for BI_LD_ATTR. But number of vector channels */
- unsigned channels;
-};
+/* For scheduling purposes this is a high latency instruction and must be at
+ * the end of a clause. Implies ADD */
+#define BI_SCHED_HI_LATENCY ((1 << 7) | BI_SCHED_ADD)
+
+/* Intrinsic is vectorized and should read 4 components regardless of writemask */
+#define BI_VECTOR (1 << 8)
+
+/* Use a data register for src0/dest respectively, bypassing the usual
+ * register accessor. Mutually exclusive. */
+#define BI_DATA_REG_SRC (1 << 9)
+#define BI_DATA_REG_DEST (1 << 10)
+
+/* It can't get any worse than csel4... can it? */
+#define BIR_SRC_COUNT 4
/* BI_LD_VARY */
struct bi_load_vary {
- /* All parameters used here. Indirect location specified in
- * src1 and ignoring location, if present. */
- struct bi_load load;
-
enum bifrost_interp_mode interp_mode;
bool reuse;
bool flat;
};
+/* BI_BRANCH encoding the details of the branch itself as well as a pointer to
+ * the target. We forward declare bi_block since this is mildly circular (not
+ * strictly, but this order of the file makes more sense I think)
+ *
+ * We define our own enum of conditions since the conditions in the hardware
+ * packed in crazy ways that would make manipulation unweildly (meaning changes
+ * based on port swapping, etc), so we defer dealing with that until emit time.
+ * Likewise, we expose NIR types instead of the crazy branch types, although
+ * the restrictions do eventually apply of course. */
+
+struct bi_block;
+
+enum bi_cond {
+ BI_COND_ALWAYS,
+ BI_COND_LT,
+ BI_COND_LE,
+ BI_COND_GE,
+ BI_COND_GT,
+ BI_COND_EQ,
+ BI_COND_NE,
+};
+
+struct bi_branch {
+ /* Types are specified in src_types and must be compatible (either both
+ * int, or both float, 16/32, and same size or 32/16 if float. Types
+ * ignored if BI_COND_ALWAYS is set for an unconditional branch. */
+
+ enum bi_cond cond;
+ struct bi_block *target;
+};
+
+/* Opcodes within a class */
+enum bi_minmax_op {
+ BI_MINMAX_MIN,
+ BI_MINMAX_MAX
+};
+
+enum bi_bitwise_op {
+ BI_BITWISE_AND,
+ BI_BITWISE_OR,
+ BI_BITWISE_XOR
+};
+
+enum bi_round_op {
+ BI_ROUND_MODE, /* use round mode */
+ BI_ROUND_ROUND /* i.e.: fround() */
+};
+
+enum bi_special_op {
+ BI_SPECIAL_FRCP,
+ BI_SPECIAL_FRSQ,
+ BI_SPECIAL_FATAN,
+ BI_SPECIAL_FSIN,
+ BI_SPECIAL_FCOS,
+ BI_SPECIAL_FEXP,
+ BI_SPECIAL_FLOG2,
+ BI_SPECIAL_FLOGE
+};
+
typedef struct {
struct list_head link; /* Must be first */
enum bi_class type;
unsigned dest;
unsigned src[BIR_SRC_COUNT];
- /* If one of the sources has BIR_INDEX_CONSTANT... */
+ /* If one of the sources has BIR_INDEX_CONSTANT */
union {
uint64_t u64;
uint32_t u32;
/* Round mode (requires BI_ROUNDMODE) */
enum bifrost_roundmode roundmode;
+ /* Writemask (bit for each affected byte). This is quite restricted --
+ * ALU ops can only write to a single channel (exception: <32 in which
+ * you can write to 32/N contiguous aligned channels). Load/store can
+ * only write to all channels at once, in a sense. But it's still
+ * better to use this generic form than have synthetic ops flying
+ * about, since we're not essentially vector for RA purposes. */
+ uint16_t writemask;
+
/* Destination type. Usually the type of the instruction
* itself, but if sources and destination have different
* types, the type of the destination wins (so f2i would be
* int). Zero if there is no destination. Bitsize included */
nir_alu_type dest_type;
+ /* Source types if required by the class */
+ nir_alu_type src_types[BIR_SRC_COUNT];
+
+ /* If the source type is 8-bit or 16-bit such that SIMD is possible,
+ * and the class has BI_SWIZZLABLE, this is a swizzle in the usual
+ * sense. On non-SIMD instructions, it can be used for component
+ * selection, so we don't have to special case extraction. */
+ uint8_t swizzle[BIR_SRC_COUNT][NIR_MAX_VEC_COMPONENTS];
+
+ /* A class-specific op from which the actual opcode can be derived
+ * (along with the above information) */
+
+ union {
+ enum bi_minmax_op minmax;
+ enum bi_bitwise_op bitwise;
+ enum bi_round_op round;
+ enum bi_special_op special;
+ enum bi_cond compare;
+ } op;
+
/* Union for class-specific information */
union {
enum bifrost_minmax_mode minmax;
- struct bi_load load;
struct bi_load_vary load_vary;
+ struct bi_branch branch;
+
+ /* For CSEL, the comparison op. BI_COND_ALWAYS doesn't make
+ * sense here but you can always just use a move for that */
+ enum bi_cond csel_cond;
+
+ /* For BLEND -- the location 0-7 */
+ unsigned blend_location;
};
} bi_instruction;
bi_instruction *instructions[16];
bi_bundle bundles[8];
};
+
+ /* For scoreboarding -- the clause ID (this is not globally unique!)
+ * and its dependencies in terms of other clauses, computed during
+ * scheduling and used when emitting code. Dependencies expressed as a
+ * bitfield matching the hardware, except shifted by a clause (the
+ * shift back to the ISA's off-by-one encoding is worked out when
+ * emitting clauses) */
+ unsigned scoreboard_id;
+ uint8_t dependencies;
+
+ /* Back-to-back corresponds directly to the back-to-back bit. Branch
+ * conditional corresponds to the branch conditional bit except that in
+ * the emitted code it's always set if back-to-bit is, whereas we use
+ * the actual value (without back-to-back so to speak) internally */
+ bool back_to_back;
+ bool branch_conditional;
+
+ /* Assigned data register */
+ unsigned data_register;
+
+ /* Corresponds to the usual bit but shifted by a clause */
+ bool data_register_write_barrier;
+
+ /* Constants read by this clause. ISA limit. */
+ uint64_t constants[8];
+ unsigned constant_count;
+
+ /* What type of high latency instruction is here, basically */
+ unsigned clause_type;
} bi_clause;
typedef struct bi_block {
- struct list_head link; /* must be first */
- unsigned name; /* Just for pretty-printing */
+ pan_block base; /* must be first */
/* If true, uses clauses; if false, uses instructions */
bool scheduled;
-
- union {
- struct list_head instructions; /* pre-schedule, list of bi_instructions */
- struct list_head clauses; /* list of bi_clause */
- };
+ struct list_head clauses; /* list of bi_clause */
} bi_block;
typedef struct {
nir_shader *nir;
+ gl_shader_stage stage;
struct list_head blocks; /* list of bi_block */
-} bi_context;
+ struct panfrost_sysvals sysvals;
+ uint32_t quirks;
+
+ /* During NIR->BIR */
+ nir_function_impl *impl;
+ bi_block *current_block;
+ unsigned block_name_count;
+ bi_block *after_block;
+ bi_block *break_block;
+ bi_block *continue_block;
+ bool emitted_atest;
+
+ /* For creating temporaries */
+ unsigned temp_alloc;
+
+ /* Analysis results */
+ bool has_liveness;
+
+ /* Stats for shader-db */
+ unsigned instruction_count;
+ unsigned loop_count;
+} bi_context;
+
+static inline bi_instruction *
+bi_emit(bi_context *ctx, bi_instruction ins)
+{
+ bi_instruction *u = rzalloc(ctx, bi_instruction);
+ memcpy(u, &ins, sizeof(ins));
+ list_addtail(&u->link, &ctx->current_block->base.instructions);
+ return u;
+}
+
+static inline void
+bi_remove_instruction(bi_instruction *ins)
+{
+ list_del(&ins->link);
+}
/* So we can distinguish between SSA/reg/sentinel quickly */
#define BIR_NO_ARG (0)
* Uniform: access a uniform register given by low bits.
* Constant: access the specified constant
* Zero: special cased to avoid wasting a constant
+ * Passthrough: a bifrost_packed_src to passthrough T/T0/T1
*/
#define BIR_INDEX_REGISTER (1 << 31)
#define BIR_INDEX_UNIFORM (1 << 30)
#define BIR_INDEX_CONSTANT (1 << 29)
#define BIR_INDEX_ZERO (1 << 28)
+#define BIR_INDEX_PASS (1 << 27)
/* Keep me synced please so we can check src & BIR_SPECIAL */
#define BIR_SPECIAL ((BIR_INDEX_REGISTER | BIR_INDEX_UNIFORM) | \
- (BIR_INDEX_CONSTANT | BIR_INDEX_ZERO)
+ (BIR_INDEX_CONSTANT | BIR_INDEX_ZERO | BIR_INDEX_PASS))
+
+static inline unsigned
+bi_max_temp(bi_context *ctx)
+{
+ unsigned alloc = MAX2(ctx->impl->reg_alloc, ctx->impl->ssa_alloc);
+ return ((alloc + 2 + ctx->temp_alloc) << 1);
+}
+
+static inline unsigned
+bi_make_temp(bi_context *ctx)
+{
+ return (ctx->impl->ssa_alloc + 1 + ctx->temp_alloc++) << 1;
+}
+
+static inline unsigned
+bi_make_temp_reg(bi_context *ctx)
+{
+ return ((ctx->impl->reg_alloc + ctx->temp_alloc++) << 1) | BIR_IS_REG;
+}
static inline unsigned
bir_ssa_index(nir_ssa_def *ssa)
}
}
+/* Iterators for Bifrost IR */
+
+#define bi_foreach_block(ctx, v) \
+ list_for_each_entry(pan_block, v, &ctx->blocks, link)
+
+#define bi_foreach_block_from(ctx, from, v) \
+ list_for_each_entry_from(pan_block, v, from, &ctx->blocks, link)
+
+#define bi_foreach_instr_in_block(block, v) \
+ list_for_each_entry(bi_instruction, v, &(block)->base.instructions, link)
+
+#define bi_foreach_instr_in_block_rev(block, v) \
+ list_for_each_entry_rev(bi_instruction, v, &(block)->base.instructions, link)
+
+#define bi_foreach_instr_in_block_safe(block, v) \
+ list_for_each_entry_safe(bi_instruction, v, &(block)->base.instructions, link)
+
+#define bi_foreach_instr_in_block_safe_rev(block, v) \
+ list_for_each_entry_safe_rev(bi_instruction, v, &(block)->base.instructions, link)
+
+#define bi_foreach_instr_in_block_from(block, v, from) \
+ list_for_each_entry_from(bi_instruction, v, from, &(block)->base.instructions, link)
+
+#define bi_foreach_instr_in_block_from_rev(block, v, from) \
+ list_for_each_entry_from_rev(bi_instruction, v, from, &(block)->base.instructions, link)
+
+#define bi_foreach_clause_in_block(block, v) \
+ list_for_each_entry(bi_clause, v, &(block)->clauses, link)
+
+#define bi_foreach_instr_global(ctx, v) \
+ bi_foreach_block(ctx, v_block) \
+ bi_foreach_instr_in_block((bi_block *) v_block, v)
+
+#define bi_foreach_instr_global_safe(ctx, v) \
+ bi_foreach_block(ctx, v_block) \
+ bi_foreach_instr_in_block_safe((bi_block *) v_block, v)
+
+/* Based on set_foreach, expanded with automatic type casts */
+
+#define bi_foreach_predecessor(blk, v) \
+ struct set_entry *_entry_##v; \
+ bi_block *v; \
+ for (_entry_##v = _mesa_set_next_entry(blk->base.predecessors, NULL), \
+ v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL); \
+ _entry_##v != NULL; \
+ _entry_##v = _mesa_set_next_entry(blk->base.predecessors, _entry_##v), \
+ v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL))
+
+#define bi_foreach_src(ins, v) \
+ for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
+
+static inline bi_instruction *
+bi_prev_op(bi_instruction *ins)
+{
+ return list_last_entry(&(ins->link), bi_instruction, link);
+}
+
+static inline bi_instruction *
+bi_next_op(bi_instruction *ins)
+{
+ return list_first_entry(&(ins->link), bi_instruction, link);
+}
+
+static inline pan_block *
+pan_next_block(pan_block *block)
+{
+ return list_first_entry(&(block->link), pan_block, link);
+}
+
+/* BIR manipulation */
+
+bool bi_has_outmod(bi_instruction *ins);
+bool bi_has_source_mods(bi_instruction *ins);
+bool bi_is_src_swizzled(bi_instruction *ins, unsigned s);
+bool bi_has_arg(bi_instruction *ins, unsigned arg);
+uint16_t bi_from_bytemask(uint16_t bytemask, unsigned bytes);
+unsigned bi_get_component_count(bi_instruction *ins);
+uint16_t bi_bytemask_of_read_components(bi_instruction *ins, unsigned node);
+
+/* BIR passes */
+
+bool bi_opt_dead_code_eliminate(bi_context *ctx, bi_block *block);
+void bi_schedule(bi_context *ctx);
+void bi_register_allocate(bi_context *ctx);
+
+/* Liveness */
+
+void bi_compute_liveness(bi_context *ctx);
+void bi_liveness_ins_update(uint16_t *live, bi_instruction *ins, unsigned max);
+void bi_invalidate_liveness(bi_context *ctx);
+bool bi_is_live_after(bi_context *ctx, bi_block *block, bi_instruction *start, int src);
+
+/* Code emit */
+
+void bi_pack(bi_context *ctx, struct util_dynarray *emission);
+
#endif
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