/* Intrinsic is vectorized and should read 4 components regardless of writemask */
#define BI_VECTOR (1 << 8)
+/* Use a data register for src0/dest respectively, bypassing the usual
+ * register accessor. Mutually exclusive. */
+#define BI_DATA_REG_SRC (1 << 9)
+#define BI_DATA_REG_DEST (1 << 10)
+
/* It can't get any worse than csel4... can it? */
#define BIR_SRC_COUNT 4
bool back_to_back;
bool branch_conditional;
+ /* Assigned data register */
+ unsigned data_register;
+
/* Corresponds to the usual bit but shifted by a clause */
bool data_register_write_barrier;
/* Constants read by this clause. ISA limit. */
uint64_t constants[8];
unsigned constant_count;
+
+ /* What type of high latency instruction is here, basically */
+ unsigned clause_type;
} bi_clause;
typedef struct bi_block {
* Uniform: access a uniform register given by low bits.
* Constant: access the specified constant
* Zero: special cased to avoid wasting a constant
+ * Passthrough: a bifrost_packed_src to passthrough T/T0/T1
*/
#define BIR_INDEX_REGISTER (1 << 31)
#define BIR_INDEX_UNIFORM (1 << 30)
#define BIR_INDEX_CONSTANT (1 << 29)
#define BIR_INDEX_ZERO (1 << 28)
+#define BIR_INDEX_PASS (1 << 27)
/* Keep me synced please so we can check src & BIR_SPECIAL */
#define BIR_SPECIAL ((BIR_INDEX_REGISTER | BIR_INDEX_UNIFORM) | \
- (BIR_INDEX_CONSTANT | BIR_INDEX_ZERO))
+ (BIR_INDEX_CONSTANT | BIR_INDEX_ZERO | BIR_INDEX_PASS))
static inline unsigned
bi_max_temp(bi_context *ctx)