pan/bi: Add CSEL.16 packing tests

[mesa.git] / src / panfrost / bifrost / disassemble.c

diff --git a/src/panfrost/bifrost/disassemble.c b/src/panfrost/bifrost/disassemble.c
index 48d6e700e3daa9ec3a00b7991b2bbb3730ef3c1e..e5f23eb0a6f0fcc1fbb2633f63871d82447516b6 100644 (file)
--- a/src/panfrost/bifrost/disassemble.c
+++ b/src/panfrost/bifrost/disassemble.c
@@ -1020,7 +1020,8 @@ static const struct add_op_info add_op_infos[] = {
         { 0x07f18, "LSHIFT_ADD_HIGH32.i32", ADD_TWO_SRC },
         { 0x08000, "LD_ATTR", ADD_LOAD_ATTR, true },
         { 0x0a000, "LD_VAR.32", ADD_VARYING_INTERP, true },
-        { 0x0b000, "TEX", ADD_TEX_COMPACT, true },
+        { 0x0b000, "TEXC", ADD_TEX_COMPACT, true },
+        { 0x0b400, "TEXC.vtx", ADD_TEX_COMPACT, true },
         { 0x0c188, "LOAD.i32", ADD_TWO_SRC, true },
         { 0x0c1a0, "LD_UBO.i32", ADD_TWO_SRC, true },
         { 0x0c1b8, "LD_SCRATCH.v2i32", ADD_TWO_SRC, true },
@@ -1070,6 +1071,7 @@ static const struct add_op_info add_op_infos[] = {
         { 0x0ea78, "SEL.YY.i16", ADD_TWO_SRC },
         { 0x0ec00, "F32_TO_F16", ADD_TWO_SRC },
         { 0x0e840, "CSEL.64",    ADD_THREE_SRC }, // u2u32(src2) ? src0 : src1
+        { 0x0e940, "CSEL.8",    ADD_THREE_SRC }, // (src2 != 0) ? src0 : src1
         { 0x0f640, "ICMP.GL.GT", ADD_TWO_SRC }, // src0 > src1 ? 1 : 0
         { 0x0f648, "ICMP.GL.GE", ADD_TWO_SRC },
         { 0x0f650, "UCMP.GL.GT", ADD_TWO_SRC },
@@ -1084,26 +1086,39 @@ static const struct add_op_info add_op_infos[] = {
         { 0x0f6d0, "UCMP.D3D.GT", ADD_TWO_SRC },
         { 0x0f6d8, "UCMP.D3D.GE", ADD_TWO_SRC },
         { 0x0f6e0, "ICMP.D3D.EQ", ADD_TWO_SRC },
+        { 0x0f700, "ICMP.64.GT.PT1", ADD_TWO_SRC },
+        { 0x0f708, "ICMP.64.GE.PT1", ADD_TWO_SRC },
+        { 0x0f710, "UCMP.64.GT.PT1", ADD_TWO_SRC },
+        { 0x0f718, "UCMP.64.GE.PT1", ADD_TWO_SRC },
+        { 0x0f720, "ICMP.64.EQ.PT1", ADD_TWO_SRC },
+        { 0x0f728, "ICMP.64.NE.PT1", ADD_TWO_SRC },
+        { 0x0f7c0, "ICMP.64.PT2", ADD_THREE_SRC }, // src3 = result of PT1
         { 0x10000, "MAX.v2f16", ADD_FMINMAX16 },
         { 0x11000, "ADD_MSCALE.f32", ADD_FADDMscale },
         { 0x12000, "MIN.v2f16", ADD_FMINMAX16 },
         { 0x14000, "ADD.v2f16", ADD_FADD16 },
+        { 0x16000, "FCMP.GL", ADD_FCMP16 },
         { 0x17000, "FCMP.D3D", ADD_FCMP16 },
         { 0x17880, "ADD.v4i8", ADD_TWO_SRC },
         { 0x178c0, "ADD.i32",  ADD_TWO_SRC },
         { 0x17900, "ADD.v2i16", ADD_TWO_SRC },
+        { 0x17a80, "SUB.v4i8", ADD_TWO_SRC },
         { 0x17ac0, "SUB.i32",  ADD_TWO_SRC },
+        { 0x17b00, "SUB.v2i16",  ADD_TWO_SRC },
         { 0x17c10, "ADDC.i32", ADD_TWO_SRC }, // adds src0 to the bottom bit of src1
         { 0x17d80, "ADD.i32.i16.X", ADD_TWO_SRC },
         { 0x17d90, "ADD.i32.u16.X", ADD_TWO_SRC },
         { 0x17dc0, "ADD.i32.i16.Y", ADD_TWO_SRC },
         { 0x17dd0, "ADD.i32.u16.Y", ADD_TWO_SRC },
-        { 0x18000, "LD_VAR_ADDR", ADD_VARYING_ADDRESS, true },
-        { 0x19181, "DISCARD.FEQ.f32", ADD_TWO_SRC, true },
-        { 0x19189, "DISCARD.FNE.f32", ADD_TWO_SRC, true },
-        { 0x1918C, "DISCARD.GL.f32", ADD_TWO_SRC, true }, /* Consumes ICMP.GL/etc with fixed 0 argument */
-        { 0x19190, "DISCARD.FLE.f32", ADD_TWO_SRC, true },
-        { 0x19198, "DISCARD.FLT.f32", ADD_TWO_SRC, true },
+        { 0x18000, "LD_VAR_ADDR", ADD_VARYING_ADDRESS, false },
+        { 0x19100, "DISCARD.FEQ.f16", ADD_TWO_SRC, false },
+        { 0x19108, "DISCARD.FNE.f16", ADD_TWO_SRC, false },
+        { 0x19110, "DISCARD.FLE.f16", ADD_TWO_SRC, false },
+        { 0x19118, "DISCARD.FLT.f16", ADD_TWO_SRC, false },
+        { 0x19180, "DISCARD.FEQ.f32", ADD_TWO_SRC, false },
+        { 0x19188, "DISCARD.FNE.f32", ADD_TWO_SRC, false },
+        { 0x19190, "DISCARD.FLE.f32", ADD_TWO_SRC, false },
+        { 0x19198, "DISCARD.FLT.f32", ADD_TWO_SRC, false },
         { 0x191e8, "ATEST.f32", ADD_TWO_SRC, true },
         { 0x191f0, "ATEST.X.f16", ADD_TWO_SRC, true },
         { 0x191f8, "ATEST.Y.f16", ADD_TWO_SRC, true },
@@ -1113,8 +1128,10 @@ static const struct add_op_info add_op_infos[] = {
         { 0x193c0, "ST_VAR.v4", ADD_THREE_SRC, true },
         { 0x1952c, "BLEND", ADD_BLENDING, true },
         { 0x1a000, "LD_VAR.16", ADD_VARYING_INTERP, true },
+        { 0x1ae20, "TEX.vtx", ADD_TEX, true },
         { 0x1ae60, "TEX", ADD_TEX, true },
-        { 0x1b000, "TEX.f16", ADD_TEX_COMPACT, true },
+        { 0x1b000, "TEXC.f16", ADD_TEX_COMPACT, true },
+        { 0x1b400, "TEXC.vtx.f16", ADD_TEX_COMPACT, true },
         { 0x1c000, "RSHIFT_NAND.i32", ADD_SHIFT },
         { 0x1c400, "RSHIFT_AND.i32", ADD_SHIFT },
         { 0x1c800, "LSHIFT_NAND.i32", ADD_SHIFT },
@@ -1414,10 +1431,9 @@ static void dump_add(FILE *fp, uint64_t word, struct bifrost_regs regs,
                 if (info.src_type == ADD_TEX_COMPACT) {
                         tex_index = (ADD.op >> 3) & 0x7;
                         sampler_index = (ADD.op >> 7) & 0x7;
-                        bool unknown = (ADD.op & 0x40);
-                        // TODO: figure out if the unknown bit is ever 0
-                        if (!unknown)
-                                fprintf(fp, "unknown ");
+                        bool compute_lod = (ADD.op & 0x40);
+                        if (!compute_lod)
+                                fprintf(fp, "vtx lod 0 ");
                 } else {
                         uint64_t constVal = get_const(consts, regs);
                         uint32_t controlBits = (ADD.op & 0x8) ? (constVal >> 32) : constVal;