#define TARGET_BREAK 1
#define TARGET_CONTINUE 2
#define TARGET_DISCARD 3
+#define TARGET_TILEBUF_WAIT 4
typedef struct midgard_branch {
/* If conditional, the condition is specified in r31.w */
};
} midgard_branch;
+#define PAN_WRITEOUT_C 1
+#define PAN_WRITEOUT_Z 2
+#define PAN_WRITEOUT_S 4
+
/* Generic in-memory data type repesenting a single logical instruction, rather
* than a single instruction group. This is the preferred form for code gen.
* Multiple midgard_insturctions will later be combined during scheduling,
/* Out of the union for csel (could maybe be fixed..) */
bool src_invert[MIR_SRC_COUNT];
+ /* If the op supports it */
+ enum midgard_roundmode roundmode;
+
/* Special fields for an ALU instruction */
midgard_reg_info registers;
bool has_inline_constant;
bool compact_branch;
- bool writeout;
- bool writeout_depth;
- bool writeout_stencil;
+ uint8_t writeout;
bool last_writeout;
/* Masks in a saneish format. One bit per channel, not packed fancy.
unsigned nr_dependencies;
BITSET_WORD *dependents;
+ /* Use this in conjunction with `type` */
+ unsigned op;
+
+ /* This refers to midgard_outmod_float or midgard_outmod_int.
+ * In case of a ALU op, use midgard_is_integer_out_op() to know which
+ * one is used.
+ * If it's a texture op, it's always midgard_outmod_float. */
+ unsigned outmod;
+
union {
midgard_load_store_word load_store;
midgard_vector_alu alu;
} midgard_bundle;
enum midgard_rt_id {
- MIDGARD_COLOR_RT0,
+ MIDGARD_COLOR_RT0 = 0,
MIDGARD_COLOR_RT1,
MIDGARD_COLOR_RT2,
MIDGARD_COLOR_RT3,
+ MIDGARD_COLOR_RT4,
+ MIDGARD_COLOR_RT5,
+ MIDGARD_COLOR_RT6,
+ MIDGARD_COLOR_RT7,
MIDGARD_ZS_RT,
MIDGARD_NUM_RTS,
};
/* Render target number for a keyed blend shader. Depends on is_blend */
unsigned blend_rt;
+ /* Index to precolour to r0 for an input blend colour */
+ unsigned blend_input;
+
+ /* Index to precolour to r2 for a dual-source blend colour */
+ unsigned blend_src1;
+
/* Tracking for blend constant patching */
int blend_constant_offset;
void mir_set_bytemask(midgard_instruction *ins, uint16_t bytemask);
signed mir_upper_override(midgard_instruction *ins, unsigned inst_size);
unsigned mir_components_for_type(nir_alu_type T);
+unsigned max_bitsize_for_alu(midgard_instruction *ins);
+midgard_reg_mode reg_mode_for_bitsize(unsigned bitsize);
/* MIR printing */
.swizzle = SWIZZLE_IDENTITY,
.dest = dest,
.dest_type = nir_type_uint32,
- .alu = {
- .op = midgard_alu_op_imov,
- .reg_mode = midgard_reg_mode_32,
- .outmod = midgard_outmod_int_wrap
- },
+ .op = midgard_alu_op_imov,
+ .outmod = midgard_outmod_int_wrap
};
return ins;
.dest = ~0,
.src = { ~0, ~0, ~0, ~0 },
.swizzle = SWIZZLE_IDENTITY_4,
+ .op = is_store ? midgard_op_st_int4 : midgard_op_ld_int4,
.load_store = {
- .op = is_store ? midgard_op_st_int4 : midgard_op_ld_int4,
-
/* For register spilling - to thread local storage */
.arg_1 = 0xEA,
.arg_2 = 0x1E,