pan/mdg: eliminate references to ins->load_store.op

[mesa.git] / src / panfrost / midgard / compiler.h

diff --git a/src/panfrost/midgard/compiler.h b/src/panfrost/midgard/compiler.h
index 9de53918644522e4c2f5cbb58f7cbc741773f397..134d1ed6d2c92530cca498cc3493acc28d58a3ce 100644 (file)
--- a/src/panfrost/midgard/compiler.h
+++ b/src/panfrost/midgard/compiler.h
@@ -51,6 +51,7 @@ struct midgard_block;
 #define TARGET_BREAK 1
 #define TARGET_CONTINUE 2
 #define TARGET_DISCARD 3
+#define TARGET_TILEBUF_WAIT 4
 
 typedef struct midgard_branch {
         /* If conditional, the condition is specified in r31.w */
@@ -70,6 +71,10 @@ typedef struct midgard_branch {
         };
 } midgard_branch;
 
+#define PAN_WRITEOUT_C 1
+#define PAN_WRITEOUT_Z 2
+#define PAN_WRITEOUT_S 4
+
 /* Generic in-memory data type repesenting a single logical instruction, rather
  * than a single instruction group. This is the preferred form for code gen.
  * Multiple midgard_insturctions will later be combined during scheduling,
@@ -101,6 +106,11 @@ typedef struct midgard_instruction {
         nir_alu_type src_types[MIR_SRC_COUNT];
         nir_alu_type dest_type;
 
+        /* Packing ops have non-32-bit dest types even though they functionally
+         * work at the 32-bit level, use this as a signal to disable copyprop.
+         * We maybe need synthetic pack ops instead. */
+        bool is_pack;
+
         /* Modifiers, depending on type */
         union {
                 struct {
@@ -116,6 +126,9 @@ typedef struct midgard_instruction {
         /* Out of the union for csel (could maybe be fixed..) */
         bool src_invert[MIR_SRC_COUNT];
 
+        /* If the op supports it */
+        enum midgard_roundmode roundmode;
+
         /* Special fields for an ALU instruction */
         midgard_reg_info registers;
 
@@ -134,9 +147,7 @@ typedef struct midgard_instruction {
         bool has_inline_constant;
 
         bool compact_branch;
-        bool writeout;
-        bool writeout_depth;
-        bool writeout_stencil;
+        uint8_t writeout;
         bool last_writeout;
 
         /* Masks in a saneish format. One bit per channel, not packed fancy.
@@ -164,8 +175,14 @@ typedef struct midgard_instruction {
         unsigned nr_dependencies;
         BITSET_WORD *dependents;
 
-        /* For load/store ops.. force 64-bit destination */
-        bool load_64;
+        /* Use this in conjunction with `type` */
+        unsigned op;
+
+        /* This refers to midgard_outmod_float or midgard_outmod_int.
+         * In case of a ALU op, use midgard_is_integer_out_op() to know which
+         * one is used.
+         * If it's a texture op, it's always midgard_outmod_float. */
+        unsigned outmod;
 
         union {
                 midgard_load_store_word load_store;
@@ -217,10 +234,14 @@ typedef struct midgard_bundle {
 } midgard_bundle;
 
 enum midgard_rt_id {
-        MIDGARD_COLOR_RT0,
+        MIDGARD_COLOR_RT0 = 0,
         MIDGARD_COLOR_RT1,
         MIDGARD_COLOR_RT2,
         MIDGARD_COLOR_RT3,
+        MIDGARD_COLOR_RT4,
+        MIDGARD_COLOR_RT5,
+        MIDGARD_COLOR_RT6,
+        MIDGARD_COLOR_RT7,
         MIDGARD_ZS_RT,
         MIDGARD_NUM_RTS,
 };
@@ -235,6 +256,12 @@ typedef struct compiler_context {
         /* Render target number for a keyed blend shader. Depends on is_blend */
         unsigned blend_rt;
 
+        /* Index to precolour to r0 for an input blend colour */
+        unsigned blend_input;
+
+        /* Index to precolour to r2 for a dual-source blend colour */
+        unsigned blend_src1;
+
         /* Tracking for blend constant patching */
         int blend_constant_offset;
 
@@ -501,6 +528,9 @@ uint16_t mir_bytemask(midgard_instruction *ins);
 uint16_t mir_round_bytemask_up(uint16_t mask, unsigned bits);
 void mir_set_bytemask(midgard_instruction *ins, uint16_t bytemask);
 signed mir_upper_override(midgard_instruction *ins, unsigned inst_size);
+unsigned mir_components_for_type(nir_alu_type T);
+unsigned max_bitsize_for_alu(midgard_instruction *ins);
+midgard_reg_mode reg_mode_for_bitsize(unsigned bitsize);
 
 /* MIR printing */
 
@@ -531,11 +561,8 @@ v_mov(unsigned src, unsigned dest)
                 .swizzle = SWIZZLE_IDENTITY,
                 .dest = dest,
                 .dest_type = nir_type_uint32,
-                .alu = {
-                        .op = midgard_alu_op_imov,
-                        .reg_mode = midgard_reg_mode_32,
-                        .outmod = midgard_outmod_int_wrap
-                },
+                .op = midgard_alu_op_imov,
+                .outmod = midgard_outmod_int_wrap
         };
 
         return ins;
@@ -568,9 +595,8 @@ v_load_store_scratch(
                 .dest = ~0,
                 .src = { ~0, ~0, ~0, ~0 },
                 .swizzle = SWIZZLE_IDENTITY_4,
+                .op = is_store ? midgard_op_st_int4 : midgard_op_ld_int4,
                 .load_store = {
-                        .op = is_store ? midgard_op_st_int4 : midgard_op_ld_int4,
-
                         /* For register spilling - to thread local storage */
                         .arg_1 = 0xEA,
                         .arg_2 = 0x1E,
@@ -643,12 +669,14 @@ void mir_analyze_helper_requirements(compiler_context *ctx);
 
 void emit_binary_bundle(
         compiler_context *ctx,
+        midgard_block *block,
         midgard_bundle *bundle,
         struct util_dynarray *emission,
         int next_tag);
 
 bool
 nir_undef_to_zero(nir_shader *shader);
+bool nir_fuse_io_16(nir_shader *shader);
 
 void midgard_nir_lod_errata(nir_shader *shader);