#define TARGET_BREAK 1
#define TARGET_CONTINUE 2
#define TARGET_DISCARD 3
+#define TARGET_TILEBUF_WAIT 4
typedef struct midgard_branch {
/* If conditional, the condition is specified in r31.w */
};
} midgard_branch;
+#define PAN_WRITEOUT_C 1
+#define PAN_WRITEOUT_Z 2
+#define PAN_WRITEOUT_S 4
+
/* Generic in-memory data type repesenting a single logical instruction, rather
* than a single instruction group. This is the preferred form for code gen.
* Multiple midgard_insturctions will later be combined during scheduling,
/* vec16 swizzle, unpacked, per source */
unsigned swizzle[MIR_SRC_COUNT][MIR_VEC_COMPONENTS];
+ /* Types! */
+ nir_alu_type src_types[MIR_SRC_COUNT];
+ nir_alu_type dest_type;
+
+ /* Packing ops have non-32-bit dest types even though they functionally
+ * work at the 32-bit level, use this as a signal to disable copyprop.
+ * We maybe need synthetic pack ops instead. */
+ bool is_pack;
+
+ /* Modifiers, depending on type */
+ union {
+ struct {
+ bool src_abs[MIR_SRC_COUNT];
+ bool src_neg[MIR_SRC_COUNT];
+ };
+
+ struct {
+ bool src_shift[MIR_SRC_COUNT];
+ };
+ };
+
+ /* Out of the union for csel (could maybe be fixed..) */
+ bool src_invert[MIR_SRC_COUNT];
+
+ /* If the op supports it */
+ enum midgard_roundmode roundmode;
+
/* Special fields for an ALU instruction */
midgard_reg_info registers;
+ /* For textures: should helpers execute this instruction (instead of
+ * just helping with derivatives)? Should helpers terminate after? */
+ bool helper_terminate;
+ bool helper_execute;
+
/* I.e. (1 << alu_bit) */
int unit;
bool has_inline_constant;
bool compact_branch;
- bool writeout;
- bool writeout_depth;
- bool writeout_stencil;
+ uint8_t writeout;
bool last_writeout;
- /* Kind of a hack, but hint against aggressive DCE */
- bool dont_eliminate;
-
/* Masks in a saneish format. One bit per channel, not packed fancy.
* Use this instead of the op specific ones, and switch over at emit
* time */
uint16_t mask;
- /* For ALU ops only: set to true to invert (bitwise NOT) the
- * destination of an integer-out op. Not implemented in hardware but
- * allows more optimizations */
-
- bool invert;
-
/* Hint for the register allocator not to spill the destination written
* from this instruction (because it is a spill/unspill node itself).
* Bitmask of spilled classes */
unsigned nr_dependencies;
BITSET_WORD *dependents;
- /* For load/store ops.. force 64-bit destination */
- bool load_64;
+ /* Use this in conjunction with `type` */
+ unsigned op;
+
+ /* This refers to midgard_outmod_float or midgard_outmod_int.
+ * In case of a ALU op, use midgard_is_integer_out_op() to know which
+ * one is used.
+ * If it's a texture op, it's always midgard_outmod_float. */
+ unsigned outmod;
union {
midgard_load_store_word load_store;
/* Indicates this is a fixed-function fragment epilogue block */
bool epilogue;
+
+ /* Are helper invocations required by this block? */
+ bool helpers_in;
} midgard_block;
typedef struct midgard_bundle {
} midgard_bundle;
enum midgard_rt_id {
- MIDGARD_COLOR_RT0,
+ MIDGARD_COLOR_RT0 = 0,
MIDGARD_COLOR_RT1,
MIDGARD_COLOR_RT2,
MIDGARD_COLOR_RT3,
+ MIDGARD_COLOR_RT4,
+ MIDGARD_COLOR_RT5,
+ MIDGARD_COLOR_RT6,
+ MIDGARD_COLOR_RT7,
MIDGARD_ZS_RT,
MIDGARD_NUM_RTS,
};
/* Render target number for a keyed blend shader. Depends on is_blend */
unsigned blend_rt;
+ /* Index to precolour to r0 for an input blend colour */
+ unsigned blend_input;
+
+ /* Index to precolour to r2 for a dual-source blend colour */
+ unsigned blend_src1;
+
/* Tracking for blend constant patching */
int blend_constant_offset;
int temp_count;
int max_hash;
+ /* Set of NIR indices that were already emitted as outmods */
+ BITSET_WORD *already_emitted;
+
/* Just the count of the max register used. Higher count => higher
* register pressure */
int work_registers;
- /* Used for cont/last hinting. Increase when a tex op is added.
- * Decrease when a tex op is removed. */
- int texture_op_count;
-
/* The number of uniforms allowable for the fast path */
int uniform_cutoff;
return IS_ALU(bundle->tag);
}
-/* Registers/SSA are distinguish in the backend by the bottom-most bit */
-
-#define IS_REG (1)
-
static inline unsigned
make_compiler_temp(compiler_context *ctx)
{
static inline unsigned
make_compiler_temp_reg(compiler_context *ctx)
{
- return ((ctx->func->impl->reg_alloc + ctx->temp_alloc++) << 1) | IS_REG;
+ return ((ctx->func->impl->reg_alloc + ctx->temp_alloc++) << 1) | PAN_IS_REG;
}
static inline unsigned
return nir_ssa_index(src->ssa);
else {
assert(!src->reg.indirect);
- return (src->reg.reg->index << 1) | IS_REG;
+ return (src->reg.reg->index << 1) | PAN_IS_REG;
}
}
-static inline unsigned
-nir_alu_src_index(compiler_context *ctx, nir_alu_src *src)
-{
- return nir_src_index(ctx, &src->src);
-}
-
static inline unsigned
nir_dest_index(nir_dest *dst)
{
return (dst->ssa.index << 1) | 0;
else {
assert(!dst->reg.indirect);
- return (dst->reg.reg->index << 1) | IS_REG;
+ return (dst->reg.reg->index << 1) | PAN_IS_REG;
}
}
void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsigned new);
void mir_rewrite_index_src_swizzle(compiler_context *ctx, unsigned old, unsigned new, unsigned *swizzle);
bool mir_single_use(compiler_context *ctx, unsigned value);
-bool mir_special_index(compiler_context *ctx, unsigned idx);
unsigned mir_use_count(compiler_context *ctx, unsigned value);
-bool mir_is_written_before(compiler_context *ctx, midgard_instruction *ins, unsigned node);
uint16_t mir_bytemask_of_read_components(midgard_instruction *ins, unsigned node);
uint16_t mir_bytemask_of_read_components_index(midgard_instruction *ins, unsigned i);
-midgard_reg_mode mir_typesize(midgard_instruction *ins);
-midgard_reg_mode mir_srcsize(midgard_instruction *ins, unsigned i);
-unsigned mir_bytes_for_mode(midgard_reg_mode mode);
-midgard_reg_mode mir_mode_for_destsize(unsigned size);
-uint16_t mir_from_bytemask(uint16_t bytemask, midgard_reg_mode mode);
+uint16_t mir_from_bytemask(uint16_t bytemask, unsigned bits);
uint16_t mir_bytemask(midgard_instruction *ins);
-uint16_t mir_round_bytemask_up(uint16_t mask, midgard_reg_mode mode);
+uint16_t mir_round_bytemask_up(uint16_t mask, unsigned bits);
void mir_set_bytemask(midgard_instruction *ins, uint16_t bytemask);
-unsigned mir_upper_override(midgard_instruction *ins);
+signed mir_upper_override(midgard_instruction *ins, unsigned inst_size);
+unsigned mir_components_for_type(nir_alu_type T);
+unsigned max_bitsize_for_alu(midgard_instruction *ins);
+midgard_reg_mode reg_mode_for_bitsize(unsigned bitsize);
/* MIR printing */
void mir_print_bundle(midgard_bundle *ctx);
void mir_print_block(midgard_block *block);
void mir_print_shader(compiler_context *ctx);
-bool mir_nontrivial_source2_mod(midgard_instruction *ins);
-bool mir_nontrivial_source2_mod_simple(midgard_instruction *ins);
+bool mir_nontrivial_mod(midgard_instruction *ins, unsigned i, bool check_swizzle);
bool mir_nontrivial_outmod(midgard_instruction *ins);
void mir_insert_instruction_before_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
.type = TAG_ALU_4,
.mask = 0xF,
.src = { ~0, src, ~0, ~0 },
+ .src_types = { 0, nir_type_uint32 },
.swizzle = SWIZZLE_IDENTITY,
.dest = dest,
- .alu = {
- .op = midgard_alu_op_imov,
- .reg_mode = midgard_reg_mode_32,
- .dest_override = midgard_dest_override_none,
- .outmod = midgard_outmod_int_wrap
- },
+ .dest_type = nir_type_uint32,
+ .op = midgard_alu_op_imov,
+ .outmod = midgard_outmod_int_wrap
};
return ins;
midgard_instruction ins = {
.type = TAG_LOAD_STORE_4,
.mask = mask,
+ .dest_type = nir_type_uint32,
.dest = ~0,
.src = { ~0, ~0, ~0, ~0 },
.swizzle = SWIZZLE_IDENTITY_4,
+ .op = is_store ? midgard_op_st_int4 : midgard_op_ld_int4,
.load_store = {
- .op = is_store ? midgard_op_st_int4 : midgard_op_ld_int4,
-
/* For register spilling - to thread local storage */
.arg_1 = 0xEA,
.arg_2 = 0x1E,
if (is_store) {
ins.src[0] = srcdest;
+ ins.src_types[0] = nir_type_uint32;
/* Ensure we are tightly swizzled so liveness analysis is
* correct */
bool mir_op_computes_derivatives(gl_shader_stage stage, unsigned op);
+void mir_analyze_helper_terminate(compiler_context *ctx);
+void mir_analyze_helper_requirements(compiler_context *ctx);
+
/* Final emission */
void emit_binary_bundle(
compiler_context *ctx,
+ midgard_block *block,
midgard_bundle *bundle,
struct util_dynarray *emission,
int next_tag);
bool
nir_undef_to_zero(nir_shader *shader);
+bool nir_fuse_io_16(nir_shader *shader);
void midgard_nir_lod_errata(nir_shader *shader);
bool midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block);
bool midgard_opt_combine_projection(compiler_context *ctx, midgard_block *block);
bool midgard_opt_varying_projection(compiler_context *ctx, midgard_block *block);
-bool midgard_opt_dead_code_eliminate(compiler_context *ctx, midgard_block *block);
+bool midgard_opt_dead_code_eliminate(compiler_context *ctx);
bool midgard_opt_dead_move_eliminate(compiler_context *ctx, midgard_block *block);
-void midgard_lower_invert(compiler_context *ctx, midgard_block *block);
-bool midgard_opt_not_propagate(compiler_context *ctx, midgard_block *block);
-bool midgard_opt_fuse_src_invert(compiler_context *ctx, midgard_block *block);
-bool midgard_opt_fuse_dest_invert(compiler_context *ctx, midgard_block *block);
-bool midgard_opt_csel_invert(compiler_context *ctx, midgard_block *block);
-bool midgard_opt_promote_fmov(compiler_context *ctx, midgard_block *block);
-bool midgard_opt_drop_cmp_invert(compiler_context *ctx, midgard_block *block);
-bool midgard_opt_invert_branch(compiler_context *ctx, midgard_block *block);
-
#endif
projects / mesa.git / blobdiff