pan/mdg: Implement raw colourbuf loads on T720

[mesa.git] / src / panfrost / midgard / compiler.h

diff --git a/src/panfrost/midgard/compiler.h b/src/panfrost/midgard/compiler.h
index 1bc93fc441ca2023d204f198d7b224ecdf6dbafe..3cb65b0a015c0f6c4dc04d0965c7c0e1908fc1fe 100644 (file)
--- a/src/panfrost/midgard/compiler.h
+++ b/src/panfrost/midgard/compiler.h
@@ -101,6 +101,26 @@ typedef struct midgard_instruction {
         nir_alu_type src_types[MIR_SRC_COUNT];
         nir_alu_type dest_type;
 
+        /* Packing ops have non-32-bit dest types even though they functionally
+         * work at the 32-bit level, use this as a signal to disable copyprop.
+         * We maybe need synthetic pack ops instead. */
+        bool is_pack;
+
+        /* Modifiers, depending on type */
+        union {
+                struct {
+                        bool src_abs[MIR_SRC_COUNT];
+                        bool src_neg[MIR_SRC_COUNT];
+                };
+
+                struct {
+                        bool src_shift[MIR_SRC_COUNT];
+                };
+        };
+
+        /* Out of the union for csel (could maybe be fixed..) */
+        bool src_invert[MIR_SRC_COUNT];
+
         /* Special fields for an ALU instruction */
         midgard_reg_info registers;
 
@@ -130,9 +150,6 @@ typedef struct midgard_instruction {
 
         uint16_t mask;
 
-        /* For accepting ALU ops - invert the nth source */
-        bool src_invert[MIR_SRC_COUNT];
-
         /* Hint for the register allocator not to spill the destination written
          * from this instruction (because it is a spill/unspill node itself).
          * Bitmask of spilled classes */
@@ -152,9 +169,6 @@ typedef struct midgard_instruction {
         unsigned nr_dependencies;
         BITSET_WORD *dependents;
 
-        /* For load/store ops.. force 64-bit destination */
-        bool load_64;
-
         union {
                 midgard_load_store_word load_store;
                 midgard_vector_alu alu;
@@ -488,7 +502,8 @@ uint16_t mir_from_bytemask(uint16_t bytemask, unsigned bits);
 uint16_t mir_bytemask(midgard_instruction *ins);
 uint16_t mir_round_bytemask_up(uint16_t mask, unsigned bits);
 void mir_set_bytemask(midgard_instruction *ins, uint16_t bytemask);
-unsigned mir_upper_override(midgard_instruction *ins);
+signed mir_upper_override(midgard_instruction *ins, unsigned inst_size);
+unsigned mir_components_for_type(nir_alu_type T);
 
 /* MIR printing */
 
@@ -496,8 +511,7 @@ void mir_print_instruction(midgard_instruction *ins);
 void mir_print_bundle(midgard_bundle *ctx);
 void mir_print_block(midgard_block *block);
 void mir_print_shader(compiler_context *ctx);
-bool mir_nontrivial_source2_mod(midgard_instruction *ins);
-bool mir_nontrivial_source2_mod_simple(midgard_instruction *ins);
+bool mir_nontrivial_mod(midgard_instruction *ins, unsigned i, bool check_swizzle);
 bool mir_nontrivial_outmod(midgard_instruction *ins);
 
 void mir_insert_instruction_before_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
@@ -523,7 +537,6 @@ v_mov(unsigned src, unsigned dest)
                 .alu = {
                         .op = midgard_alu_op_imov,
                         .reg_mode = midgard_reg_mode_32,
-                        .dest_override = midgard_dest_override_none,
                         .outmod = midgard_outmod_int_wrap
                 },
         };
@@ -649,6 +662,5 @@ bool midgard_opt_combine_projection(compiler_context *ctx, midgard_block *block)
 bool midgard_opt_varying_projection(compiler_context *ctx, midgard_block *block);
 bool midgard_opt_dead_code_eliminate(compiler_context *ctx);
 bool midgard_opt_dead_move_eliminate(compiler_context *ctx, midgard_block *block);
-bool midgard_opt_promote_fmov(compiler_context *ctx, midgard_block *block);
 
 #endif