* emitted before the register allocation pass.
*/
-#define MIR_SRC_COUNT 3
+#define MIR_SRC_COUNT 4
#define MIR_VEC_COMPONENTS 16
typedef struct midgard_instruction {
/* Instruction arguments represented as block-local SSA
* indices, rather than registers. ~0 means unused. */
- unsigned src[3];
+ unsigned src[MIR_SRC_COUNT];
unsigned dest;
/* vec16 swizzle, unpacked, per source */
uint16_t mask;
/* For ALU ops only: set to true to invert (bitwise NOT) the
- * destination of an integer-out op. Not imeplemented in hardware but
+ * destination of an integer-out op. Not implemented in hardware but
* allows more optimizations */
bool invert;
midgard_instruction ins = {
.type = TAG_ALU_4,
.mask = 0xF,
- .src = { SSA_UNUSED, src, SSA_UNUSED },
+ .src = { ~0, src, ~0, ~0 },
.swizzle = SWIZZLE_IDENTITY,
.dest = dest,
.alu = {
.type = TAG_LOAD_STORE_4,
.mask = mask,
.dest = ~0,
- .src = { ~0, ~0, ~0 },
+ .src = { ~0, ~0, ~0, ~0 },
.swizzle = SWIZZLE_IDENTITY_4,
.load_store = {
.op = is_store ? midgard_op_st_int4 : midgard_op_ld_int4,
bool midgard_opt_fuse_dest_invert(compiler_context *ctx, midgard_block *block);
bool midgard_opt_csel_invert(compiler_context *ctx, midgard_block *block);
bool midgard_opt_promote_fmov(compiler_context *ctx, midgard_block *block);
+bool midgard_opt_drop_cmp_invert(compiler_context *ctx, midgard_block *block);
#endif