pan/mdg: Ensure we don't DCE into impossible masks

[mesa.git] / src / panfrost / midgard / compiler.h

diff --git a/src/panfrost/midgard/compiler.h b/src/panfrost/midgard/compiler.h
index 618c0d792655f05ff6ae5c89986416a1e1cf8db6..c26f82613f8aa3c41e0bf27d7fa50612ea0d4f33 100644 (file)
--- a/src/panfrost/midgard/compiler.h
+++ b/src/panfrost/midgard/compiler.h
@@ -101,6 +101,21 @@ typedef struct midgard_instruction {
         nir_alu_type src_types[MIR_SRC_COUNT];
         nir_alu_type dest_type;
 
+        /* Modifiers, depending on type */
+        union {
+                struct {
+                        bool src_abs[MIR_SRC_COUNT];
+                        bool src_neg[MIR_SRC_COUNT];
+                };
+
+                struct {
+                        bool src_shift[MIR_SRC_COUNT];
+                };
+        };
+
+        /* Out of the union for csel (could maybe be fixed..) */
+        bool src_invert[MIR_SRC_COUNT];
+
         /* Special fields for an ALU instruction */
         midgard_reg_info registers;
 
@@ -130,9 +145,6 @@ typedef struct midgard_instruction {
 
         uint16_t mask;
 
-        /* For accepting ALU ops - invert the nth source */
-        bool src_invert[MIR_SRC_COUNT];
-
         /* Hint for the register allocator not to spill the destination written
          * from this instruction (because it is a spill/unspill node itself).
          * Bitmask of spilled classes */
@@ -152,9 +164,6 @@ typedef struct midgard_instruction {
         unsigned nr_dependencies;
         BITSET_WORD *dependents;
 
-        /* For load/store ops.. force 64-bit destination */
-        bool load_64;
-
         union {
                 midgard_load_store_word load_store;
                 midgard_vector_alu alu;
@@ -481,19 +490,15 @@ void mir_rewrite_index_dst_single(midgard_instruction *ins, unsigned old, unsign
 void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsigned new);
 void mir_rewrite_index_src_swizzle(compiler_context *ctx, unsigned old, unsigned new, unsigned *swizzle);
 bool mir_single_use(compiler_context *ctx, unsigned value);
-bool mir_special_index(compiler_context *ctx, unsigned idx);
 unsigned mir_use_count(compiler_context *ctx, unsigned value);
 uint16_t mir_bytemask_of_read_components(midgard_instruction *ins, unsigned node);
 uint16_t mir_bytemask_of_read_components_index(midgard_instruction *ins, unsigned i);
-midgard_reg_mode mir_typesize(midgard_instruction *ins);
-midgard_reg_mode mir_srcsize(midgard_instruction *ins, unsigned i);
-unsigned mir_bytes_for_mode(midgard_reg_mode mode);
-midgard_reg_mode mir_mode_for_destsize(unsigned size);
-uint16_t mir_from_bytemask(uint16_t bytemask, midgard_reg_mode mode);
+uint16_t mir_from_bytemask(uint16_t bytemask, unsigned bits);
 uint16_t mir_bytemask(midgard_instruction *ins);
-uint16_t mir_round_bytemask_up(uint16_t mask, midgard_reg_mode mode);
+uint16_t mir_round_bytemask_up(uint16_t mask, unsigned bits);
 void mir_set_bytemask(midgard_instruction *ins, uint16_t bytemask);
-unsigned mir_upper_override(midgard_instruction *ins);
+signed mir_upper_override(midgard_instruction *ins, unsigned inst_size);
+unsigned mir_components_for_type(nir_alu_type T);
 
 /* MIR printing */
 
@@ -501,8 +506,7 @@ void mir_print_instruction(midgard_instruction *ins);
 void mir_print_bundle(midgard_bundle *ctx);
 void mir_print_block(midgard_block *block);
 void mir_print_shader(compiler_context *ctx);
-bool mir_nontrivial_source2_mod(midgard_instruction *ins);
-bool mir_nontrivial_source2_mod_simple(midgard_instruction *ins);
+bool mir_nontrivial_mod(midgard_instruction *ins, unsigned i, bool check_swizzle);
 bool mir_nontrivial_outmod(midgard_instruction *ins);
 
 void mir_insert_instruction_before_scheduled(compiler_context *ctx, midgard_block *block, midgard_instruction *tag, midgard_instruction ins);
@@ -528,7 +532,6 @@ v_mov(unsigned src, unsigned dest)
                 .alu = {
                         .op = midgard_alu_op_imov,
                         .reg_mode = midgard_reg_mode_32,
-                        .dest_override = midgard_dest_override_none,
                         .outmod = midgard_outmod_int_wrap
                 },
         };
@@ -559,6 +562,7 @@ v_load_store_scratch(
         midgard_instruction ins = {
                 .type = TAG_LOAD_STORE_4,
                 .mask = mask,
+                .dest_type = nir_type_uint32,
                 .dest = ~0,
                 .src = { ~0, ~0, ~0, ~0 },
                 .swizzle = SWIZZLE_IDENTITY_4,
@@ -578,6 +582,7 @@ v_load_store_scratch(
 
         if (is_store) {
                 ins.src[0] = srcdest;
+                ins.src_types[0] = nir_type_uint32;
 
                 /* Ensure we are tightly swizzled so liveness analysis is
                  * correct */
@@ -650,8 +655,7 @@ void midgard_nir_lod_errata(nir_shader *shader);
 bool midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block);
 bool midgard_opt_combine_projection(compiler_context *ctx, midgard_block *block);
 bool midgard_opt_varying_projection(compiler_context *ctx, midgard_block *block);
-bool midgard_opt_dead_code_eliminate(compiler_context *ctx, midgard_block *block);
+bool midgard_opt_dead_code_eliminate(compiler_context *ctx);
 bool midgard_opt_dead_move_eliminate(compiler_context *ctx, midgard_block *block);
-bool midgard_opt_promote_fmov(compiler_context *ctx, midgard_block *block);
 
 #endif