pan/midgard: Decontextualize midgard_nir_assign_sysval_body

[mesa.git] / src / panfrost / midgard / compiler.h

diff --git a/src/panfrost/midgard/compiler.h b/src/panfrost/midgard/compiler.h
index ab9cc819ef6aee927dd7e1455c3625fc7438207c..cbe045b09a9753bcbc84cb54756a280f2edd0b44 100644 (file)
--- a/src/panfrost/midgard/compiler.h
+++ b/src/panfrost/midgard/compiler.h
@@ -38,6 +38,7 @@
 #include "main/mtypes.h"
 #include "compiler/nir_types.h"
 #include "compiler/nir/nir.h"
+#include "panfrost/util/pan_ir.h"
 
 /* Forward declare */
 struct midgard_block;
@@ -103,13 +104,15 @@ typedef struct midgard_instruction {
         int unit;
 
         bool has_constants;
-        uint32_t constants[4];
+        midgard_constants constants;
         uint16_t inline_constant;
         bool has_blend_constant;
         bool has_inline_constant;
 
         bool compact_branch;
         bool writeout;
+        bool writeout_depth;
+        bool writeout_stencil;
         bool last_writeout;
 
         /* Kind of a hack, but hint against aggressive DCE */
@@ -217,11 +220,27 @@ typedef struct midgard_bundle {
         int padding;
         int control;
         bool has_embedded_constants;
-        float constants[4];
+        midgard_constants constants;
         bool has_blend_constant;
         bool last_writeout;
 } midgard_bundle;
 
+enum midgard_rt_id {
+        MIDGARD_COLOR_RT0,
+        MIDGARD_COLOR_RT1,
+        MIDGARD_COLOR_RT2,
+        MIDGARD_COLOR_RT3,
+        MIDGARD_ZS_RT,
+        MIDGARD_NUM_RTS,
+};
+
+struct panfrost_sysvals {
+        /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
+        unsigned sysvals[MAX_SYSVAL_COUNT];
+        unsigned sysval_count;
+        struct hash_table_u64 *sysval_to_id;
+};
+
 typedef struct compiler_context {
         nir_shader *nir;
         gl_shader_stage stage;
@@ -295,11 +314,6 @@ typedef struct compiler_context {
 
         unsigned quadword_count;
 
-        /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
-        unsigned sysvals[MAX_SYSVAL_COUNT];
-        unsigned sysval_count;
-        struct hash_table_u64 *sysval_to_id;
-
         /* Bitmask of valid metadata */
         unsigned metadata;
 
@@ -307,7 +321,9 @@ typedef struct compiler_context {
         uint32_t quirks;
 
         /* Writeout instructions for each render target */
-        midgard_instruction *writeout_branch[4];
+        midgard_instruction *writeout_branch[MIDGARD_NUM_RTS];
+
+        struct panfrost_sysvals sysvals;
 } compiler_context;
 
 /* Per-block live_in/live_out */
@@ -367,12 +383,6 @@ mir_next_op(struct midgard_instruction *ins)
 #define mir_foreach_block_from(ctx, from, v) \
         list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
 
-#define mir_foreach_instr(ctx, v) \
-        list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
-
-#define mir_foreach_instr_safe(ctx, v) \
-        list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
-
 #define mir_foreach_instr_in_block(block, v) \
         list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
 #define mir_foreach_instr_in_block_rev(block, v) \
@@ -468,7 +478,7 @@ mir_exit_block(struct compiler_context *ctx)
 static inline bool
 mir_is_alu_bundle(midgard_bundle *bundle)
 {
-        return midgard_word_types[bundle->tag] == midgard_word_type_alu;
+        return IS_ALU(bundle->tag);
 }
 
 /* Registers/SSA are distinguish in the backend by the bottom-most bit */
@@ -487,11 +497,17 @@ make_compiler_temp_reg(compiler_context *ctx)
         return ((ctx->func->impl->reg_alloc + ctx->temp_alloc++) << 1) | IS_REG;
 }
 
+static inline unsigned
+nir_ssa_index(nir_ssa_def *ssa)
+{
+        return (ssa->index << 1) | 0;
+}
+
 static inline unsigned
 nir_src_index(compiler_context *ctx, nir_src *src)
 {
         if (src->is_ssa)
-                return (src->ssa->index << 1) | 0;
+                return nir_ssa_index(src->ssa);
         else {
                 assert(!src->reg.indirect);
                 return (src->reg.reg->index << 1) | IS_REG;
@@ -505,7 +521,7 @@ nir_alu_src_index(compiler_context *ctx, nir_alu_src *src)
 }
 
 static inline unsigned
-nir_dest_index(compiler_context *ctx, nir_dest *dst)
+nir_dest_index(nir_dest *dst)
 {
         if (dst->is_ssa)
                 return (dst->ssa.index << 1) | 0;
@@ -530,12 +546,12 @@ bool mir_special_index(compiler_context *ctx, unsigned idx);
 unsigned mir_use_count(compiler_context *ctx, unsigned value);
 bool mir_is_written_before(compiler_context *ctx, midgard_instruction *ins, unsigned node);
 uint16_t mir_bytemask_of_read_components(midgard_instruction *ins, unsigned node);
+uint16_t mir_bytemask_of_read_components_index(midgard_instruction *ins, unsigned i);
 midgard_reg_mode mir_typesize(midgard_instruction *ins);
 midgard_reg_mode mir_srcsize(midgard_instruction *ins, unsigned i);
 unsigned mir_bytes_for_mode(midgard_reg_mode mode);
 midgard_reg_mode mir_mode_for_destsize(unsigned size);
 uint16_t mir_from_bytemask(uint16_t bytemask, midgard_reg_mode mode);
-uint16_t mir_to_bytemask(midgard_reg_mode mode, unsigned mask);
 uint16_t mir_bytemask(midgard_instruction *ins);
 uint16_t mir_round_bytemask_up(uint16_t mask, midgard_reg_mode mode);
 void mir_set_bytemask(midgard_instruction *ins, uint16_t bytemask);
@@ -556,6 +572,8 @@ void mir_insert_instruction_after_scheduled(compiler_context *ctx, midgard_block
 void mir_flip(midgard_instruction *ins);
 void mir_compute_temp_count(compiler_context *ctx);
 
+void mir_set_offset(compiler_context *ctx, midgard_instruction *ins, nir_src *offset, bool is_shared);
+
 /* 'Intrinsic' move for aliasing */
 
 static inline midgard_instruction
@@ -616,7 +634,7 @@ v_load_store_scratch(
                 .no_spill = (1 << REG_CLASS_WORK)
         };
 
-        ins.constants[0] = byte;
+        ins.constants.u32[0] = byte;
 
         if (is_store) {
                 ins.src[0] = srcdest;
@@ -663,9 +681,6 @@ bool mir_is_live_after(compiler_context *ctx, midgard_block *block, midgard_inst
 void mir_create_pipeline_registers(compiler_context *ctx);
 void midgard_promote_uniforms(compiler_context *ctx);
 
-void
-emit_sysval_read(compiler_context *ctx, nir_instr *instr, signed dest_override, unsigned nr_components);
-
 void
 midgard_emit_derivatives(compiler_context *ctx, nir_alu_instr *instr);