pan/midgard: Pass shader stage to disassembler

[mesa.git] / src / panfrost / midgard / disassemble.c

diff --git a/src/panfrost/midgard/disassemble.c b/src/panfrost/midgard/disassemble.c
index df75730a5f906b4dd4af0a999ad9fa375a56309b..718eb9b71a582e9bae6fd68c3f3ecc73c610bd96 100644 (file)
--- a/src/panfrost/midgard/disassemble.c
+++ b/src/panfrost/midgard/disassemble.c
@@ -354,9 +354,21 @@ print_vector_src(unsigned src_binary,
         print_reg(reg, bits);
 
         //swizzle
-        if (bits == 16)
-                print_swizzle_vec8(src->swizzle, src->rep_high, src->rep_low);
-        else if (bits == 8)
+        if (bits == 16) {
+                /* When the mode of the instruction is itself 16-bit,
+                 * rep_low/high work more or less as expected. But if the mode
+                 * is 32-bit and we're stepping down, you only have vec4 and
+                 * the meaning shifts to rep_low as higher-half and rep_high is
+                 * never seen. TODO: are other modes similar? */
+
+                if (mode == midgard_reg_mode_32) {
+                        printf(".");
+                        print_swizzle_helper(src->swizzle, src->rep_low);
+                        assert(!src->rep_high);
+                } else {
+                        print_swizzle_vec8(src->swizzle, src->rep_high, src->rep_low);
+                }
+        } else if (bits == 8)
                 print_swizzle_vec16(src->swizzle, src->rep_high, src->rep_low, override);
         else if (bits == 32)
                 print_swizzle_vec4(src->swizzle, src->rep_high, src->rep_low);
@@ -502,19 +514,25 @@ print_mask(uint8_t mask, unsigned bits, midgard_dest_override override)
 }
 
 /* Prints the 4-bit masks found in texture and load/store ops, as opposed to
- * the 8-bit masks found in (vector) ALU ops */
+ * the 8-bit masks found in (vector) ALU ops. Supports texture-style 16-bit
+ * mode as well, but not load/store-style 16-bit mode. */
 
 static void
-print_mask_4(unsigned mask)
+print_mask_4(unsigned mask, bool upper)
 {
-        if (mask == 0xF) return;
+        if (mask == 0xF) {
+                if (upper)
+                        printf("'");
+
+                return;
+        }
 
         printf(".");
 
         for (unsigned i = 0; i < 4; ++i) {
                 bool a = (mask & (1 << i)) != 0;
                 if (a)
-                        printf("%c", components[i]);
+                        printf("%c", components[i + (upper ? 4 : 0)]);
         }
 }
 
@@ -1101,7 +1119,7 @@ print_load_store_instr(uint64_t data,
         }
 
         printf(" r%u", word->reg);
-        print_mask_4(word->mask);
+        print_mask_4(word->mask, false);
 
         if (!OP_IS_STORE(word->op))
                 update_dest(word->reg);
@@ -1151,29 +1169,6 @@ print_load_store_word(uint32_t *word, unsigned tabs)
         }
 }
 
-static void
-print_texture_reg(bool full, bool select, bool upper)
-{
-        if (full)
-                printf("r%d", REG_TEX_BASE + select);
-        else
-                printf("hr%d", (REG_TEX_BASE + select) * 2 + upper);
-
-        if (full && upper)
-                printf("// error: out full / upper mutually exclusive\n");
-
-}
-
-static void
-print_texture_reg_triple(unsigned triple)
-{
-        bool full = triple & 1;
-        bool select = triple & 2;
-        bool upper = triple & 4;
-
-        print_texture_reg(full, select, upper);
-}
-
 static void
 print_texture_reg_select(uint8_t u)
 {
@@ -1314,10 +1309,10 @@ print_texture_word(uint32_t *word, unsigned tabs)
         /* Output modifiers are always interpreted floatly */
         print_outmod(texture->outmod, false);
 
-        printf(" ");
-
-        print_texture_reg(texture->out_full, texture->out_reg_select, texture->out_upper);
-        print_mask_4(texture->mask);
+        printf(" %sr%d", texture->out_full ? "" : "h",
+                        REG_TEX_BASE + texture->out_reg_select);
+        print_mask_4(texture->mask, texture->out_upper);
+        assert(!(texture->out_full && texture->out_upper));
         printf(", ");
 
         /* Depending on whether we read from textures directly or indirectly,
@@ -1350,9 +1345,13 @@ print_texture_word(uint32_t *word, unsigned tabs)
         }
 
         print_swizzle_vec4(texture->swizzle, false, false);
-        printf(", ");
+        printf(", %sr%d", texture->in_reg_full ? "" : "h", REG_TEX_BASE + texture->in_reg_select);
+        assert(!(texture->in_reg_full && texture->in_reg_upper));
+
+        /* TODO: integrate with swizzle */
+        if (texture->in_reg_upper)
+                printf("'");
 
-        print_texture_reg(texture->in_reg_full, texture->in_reg_select, texture->in_reg_upper);
         print_swizzle_vec4(texture->in_reg_swizzle, false, false);
 
         /* There is *always* an offset attached. Of
@@ -1367,7 +1366,17 @@ print_texture_word(uint32_t *word, unsigned tabs)
 
         if (texture->offset_register) {
                 printf(" + ");
-                print_texture_reg_triple(texture->offset_x);
+
+                bool full = texture->offset_x & 1;
+                bool select = texture->offset_x & 2;
+                bool upper = texture->offset_x & 4;
+
+                printf("%sr%d", full ? "" : "h", REG_TEX_BASE + select);
+                assert(!(texture->out_full && texture->out_upper));
+
+                /* TODO: integrate with swizzle */
+                if (upper)
+                        printf("'");
 
                 /* The less questions you ask, the better. */
 
@@ -1455,7 +1464,7 @@ print_texture_word(uint32_t *word, unsigned tabs)
 }
 
 struct midgard_disasm_stats
-disassemble_midgard(uint8_t *code, size_t size)
+disassemble_midgard(uint8_t *code, size_t size, unsigned gpu_id, gl_shader_stage stage)
 {
         uint32_t *words = (uint32_t *) code;
         unsigned num_words = size / 4;