#include <stdio.h>
#include <stdint.h>
+#include <stdlib.h>
#include <assert.h>
#include <inttypes.h>
#include <ctype.h>
#include <string.h>
#include "midgard.h"
-#include "midgard-parse.h"
#include "midgard_ops.h"
+#include "midgard_quirks.h"
#include "disassemble.h"
#include "helpers.h"
#include "util/half_float.h"
#define DEFINE_CASE(define, str) case define: { printf(str); break; }
+static unsigned *midg_tags;
static bool is_instruction_int = false;
/* Stats */
break;
case midgard_word_type_alu:
- printf("alu%d/%X", midgard_word_size[tag], tag);
+ printf("alu%u/%X", midgard_word_size[tag], tag);
break;
default:
static void
print_ld_st_opcode(midgard_load_store_op op)
{
- if (load_store_opcode_names[op])
- printf("%s", load_store_opcode_names[op]);
+ if (load_store_opcode_props[op].name)
+ printf("%s", load_store_opcode_props[op].name);
else
printf("ldst_op_%02X", op);
}
}
}
+/* For static analysis to ensure all registers are written at least once before
+ * use along the source code path (TODO: does this break done for complex CF?)
+ */
+
+uint16_t midg_ever_written = 0;
+
static void
print_reg(unsigned reg, unsigned bits)
{
is_embedded_constant_half = (bits < 32);
}
+ unsigned uniform_reg = 23 - reg;
+ bool is_uniform = false;
+
+ /* For r8-r15, it could be a work or uniform. We distinguish based on
+ * the fact work registers are ALWAYS written before use, but uniform
+ * registers are NEVER written before use. */
+
+ if ((reg >= 8 && reg < 16) && !(midg_ever_written & (1 << reg)))
+ is_uniform = true;
+
+ /* r16-r23 are always uniform */
+
+ if (reg >= 16 && reg <= 23)
+ is_uniform = true;
+
+ /* Update the uniform count appropriately */
+
+ if (is_uniform)
+ midg_stats.uniform_count =
+ MAX2(uniform_reg + 1, midg_stats.uniform_count);
+
char prefix = prefix_for_bits(bits);
if (prefix)
print_swizzle_helper_8(swizzle, false);
} else {
print_swizzle_helper_8(swizzle, rep_high & 1);
- print_swizzle_helper_8(swizzle, !rep_low & 1);
+ print_swizzle_helper_8(swizzle, !(rep_low & 1));
}
}
printf(".");
print_swizzle_helper(swizzle, rep_high & 1);
- print_swizzle_helper(swizzle, !rep_low & 1);
+ print_swizzle_helper(swizzle, !(rep_low & 1));
}
static void
print_reg(reg, bits);
//swizzle
- if (bits == 16)
- print_swizzle_vec8(src->swizzle, src->rep_high, src->rep_low);
- else if (bits == 8)
+ if (bits == 16) {
+ /* When the mode of the instruction is itself 16-bit,
+ * rep_low/high work more or less as expected. But if the mode
+ * is 32-bit and we're stepping down, you only have vec4 and
+ * the meaning shifts to rep_low as higher-half and rep_high is
+ * never seen. TODO: are other modes similar? */
+
+ if (mode == midgard_reg_mode_32) {
+ printf(".");
+ print_swizzle_helper(src->swizzle, src->rep_low);
+ assert(!src->rep_high);
+ } else {
+ print_swizzle_vec8(src->swizzle, src->rep_high, src->rep_low);
+ }
+ } else if (bits == 8)
print_swizzle_vec16(src->swizzle, src->rep_high, src->rep_low, override);
else if (bits == 32)
print_swizzle_vec4(src->swizzle, src->rep_high, src->rep_low);
/* Since we wrapped with a function-looking thing */
if (is_int && int_mod == midgard_int_shift)
- printf(") << %d", bits);
+ printf(") << %u", bits);
else if ((is_int && (int_mod != midgard_int_normal))
|| (!is_int && src->mod & MIDGARD_FLOAT_MOD_ABS))
printf(")");
print_immediate(uint16_t imm)
{
if (is_instruction_int)
- printf("#%d", imm);
+ printf("#%u", imm);
else
printf("#%g", _mesa_half_to_float(imm));
}
-static unsigned
+static void
+update_dest(unsigned reg)
+{
+ /* We should record writes as marking this as a work register. Store
+ * the max register in work_count; we'll add one at the end */
+
+ if (reg < 16) {
+ midg_stats.work_count = MAX2(reg, midg_stats.work_count);
+ midg_ever_written |= (1 << reg);
+ }
+}
+
+static void
print_dest(unsigned reg, midgard_reg_mode mode, midgard_dest_override override)
{
/* Depending on the mode and override, we determine the type of
if (override != midgard_dest_override_none)
bits /= 2;
+ update_dest(reg);
print_reg(reg, bits);
-
- return bits;
}
static void
{
printf(".");
- if (override == midgard_dest_override_none) {
- for (unsigned i = 0; i < 8; i++) {
- if (mask & (1 << i))
- printf("%c%c",
- components[i*2 + 0],
- components[i*2 + 1]);
- }
- } else {
- bool upper = (override == midgard_dest_override_upper);
-
- for (unsigned i = 0; i < 8; i++) {
- if (mask & (1 << i))
- printf("%c", components[i + (upper ? 8 : 0)]);
- }
+ for (unsigned i = 0; i < 8; i++) {
+ if (mask & (1 << i))
+ printf("%c%c",
+ components[i*2 + 0],
+ components[i*2 + 1]);
}
}
return;
}
- if (bits < 16) {
- /* Shouldn't happen but with junk / out-of-spec shaders it
- * would cause an infinite loop */
-
- printf("/* XXX: bits = %d */", bits);
- return;
- }
-
/* Skip 'complete' masks */
- if (bits >= 32 && mask == 0xFF) return;
-
- if (bits == 16) {
- if (mask == 0x0F)
- return;
- else if (mask == 0xF0) {
- printf("'");
- return;
+ if (override == midgard_dest_override_none) {
+ if (bits >= 32 && mask == 0xFF) return;
+
+ if (bits == 16) {
+ if (mask == 0x0F)
+ return;
+ else if (mask == 0xF0) {
+ printf("'");
+ return;
+ }
}
}
bool uppercase = bits > 32;
bool tripped = false;
+ /* To apply an upper destination override, we "shift" the alphabet.
+ * E.g. with an upper override on 32-bit, instead of xyzw, print efgh.
+ * For upper 16-bit, instead of xyzwefgh, print ijklmnop */
+
+ const char *alphabet = components;
+
+ if (override == midgard_dest_override_upper)
+ alphabet += (128 / bits);
+
for (unsigned i = 0; i < 8; i += skip) {
bool a = (mask & (1 << i)) != 0;
}
if (a) {
- char c = components[i / skip];
+ char c = alphabet[i / skip];
if (uppercase)
c = toupper(c);
}
/* Prints the 4-bit masks found in texture and load/store ops, as opposed to
- * the 8-bit masks found in (vector) ALU ops */
+ * the 8-bit masks found in (vector) ALU ops. Supports texture-style 16-bit
+ * mode as well, but not load/store-style 16-bit mode. */
static void
-print_mask_4(unsigned mask)
+print_mask_4(unsigned mask, bool upper)
{
- if (mask == 0xF) return;
+ if (mask == 0xF) {
+ if (upper)
+ printf("'");
+
+ return;
+ }
printf(".");
for (unsigned i = 0; i < 4; ++i) {
bool a = (mask & (1 << i)) != 0;
if (a)
- printf("%c", components[i]);
+ printf("%c", components[i + (upper ? 4 : 0)]);
}
}
uint8_t mask = alu_field->mask;
/* First, print the destination */
- unsigned dest_size =
- print_dest(reg_info->out_reg, mode, alu_field->dest_override);
-
- /* Apply the destination override to the mask */
-
- if (mode == midgard_reg_mode_32 || mode == midgard_reg_mode_64) {
- if (override == midgard_dest_override_lower)
- mask &= 0x0F;
- else if (override == midgard_dest_override_upper)
- mask &= 0xF0;
- } else if (mode == midgard_reg_mode_16
- && override == midgard_dest_override_lower) {
- /* stub */
- }
+ print_dest(reg_info->out_reg, mode, alu_field->dest_override);
if (override != midgard_dest_override_none) {
bool modeable = (mode != midgard_reg_mode_8);
bool known = override != 0x3; /* Unused value */
if (!(modeable && known))
- printf("/* do%d */ ", override);
+ printf("/* do%u */ ", override);
}
- print_mask(mask, dest_size, override);
+ print_mask(mask, bits_for_mode(mode), override);
printf(", ");
printf(" ");
bool full = alu_field->output_full;
+ update_dest(reg_info->out_reg);
print_reg(reg_info->out_reg, full ? 32 : 16);
unsigned c = alu_field->output_component;
}
static void
-print_branch_op(int op)
+print_branch_op(unsigned op)
{
switch (op) {
case midgard_jmp_writeout_op_branch_uncond:
break;
default:
- printf("unk%d.", op);
+ printf("unk%u.", op);
break;
}
}
}
}
-static void
+static bool
print_compact_branch_writeout_field(uint16_t word)
{
midgard_jmp_writeout_op op = word & 0x7;
+ midg_stats.instruction_count++;
switch (op) {
case midgard_jmp_writeout_op_branch_uncond: {
printf("br.uncond ");
if (br_uncond.unknown != 1)
- printf("unknown:%d, ", br_uncond.unknown);
+ printf("unknown:%u, ", br_uncond.unknown);
if (br_uncond.offset >= 0)
printf("+");
print_tag_short(br_uncond.dest_tag);
printf("\n");
- break;
+ return br_uncond.offset >= 0;
}
case midgard_jmp_writeout_op_branch_cond:
print_tag_short(br_cond.dest_tag);
printf("\n");
- break;
+ return br_cond.offset >= 0;
}
}
- midg_stats.instruction_count++;
+ return false;
}
-static void
-print_extended_branch_writeout_field(uint8_t *words)
+static bool
+print_extended_branch_writeout_field(uint8_t *words, unsigned next)
{
midgard_branch_extended br;
memcpy((char *) &br, (char *) words, sizeof(br));
printf("lut%X", br.cond);
if (br.unknown)
- printf(".unknown%d", br.unknown);
+ printf(".unknown%u", br.unknown);
printf(" ");
print_tag_short(br.dest_tag);
printf("\n");
+ unsigned I = next + br.offset * 4;
+
+ if (midg_tags[I] && midg_tags[I] != br.dest_tag) {
+ printf("\t/* XXX TAG ERROR: jumping to ");
+ print_tag_short(br.dest_tag);
+ printf(" but tagged ");
+ print_tag_short(midg_tags[I]);
+ printf(" */\n");
+ }
+
+ midg_tags[I] = br.dest_tag;
+
midg_stats.instruction_count++;
+ return br.offset >= 0;
}
static unsigned
return v.f;
}
-static void
+static bool
print_alu_word(uint32_t *words, unsigned num_quad_words,
- unsigned tabs)
+ unsigned tabs, unsigned next)
{
uint32_t control_word = words[0];
uint16_t *beginning_ptr = (uint16_t *)(words + 1);
unsigned num_fields = num_alu_fields_enabled(control_word);
uint16_t *word_ptr = beginning_ptr + num_fields;
unsigned num_words = 2 + num_fields;
+ bool branch_forward = false;
if ((control_word >> 16) & 1)
printf("unknown bit 16 enabled\n");
if ((control_word >> 25) & 1) {
print_vector_field("lut", word_ptr, *beginning_ptr, tabs);
- beginning_ptr += 1;
word_ptr += 3;
num_words += 3;
}
if ((control_word >> 26) & 1) {
- print_compact_branch_writeout_field(*word_ptr);
+ branch_forward |= print_compact_branch_writeout_field(*word_ptr);
word_ptr += 1;
num_words += 1;
}
if ((control_word >> 27) & 1) {
- print_extended_branch_writeout_field((uint8_t *) word_ptr);
+ branch_forward |= print_extended_branch_writeout_field((uint8_t *) word_ptr, next);
word_ptr += 3;
num_words += 3;
}
sconsts[2],
sconsts[3]);
} else {
- int32_t *iconsts = (int32_t *) consts;
- printf("iconstants %d, %d, %d, %d\n",
+ uint32_t *iconsts = (uint32_t *) consts;
+ printf("iconstants 0x%X, 0x%X, 0x%X, 0x%X\n",
iconsts[0],
iconsts[1],
iconsts[2],
}
}
+
+ return branch_forward;
}
static void
}
if (param.zero0 || param.zero1 || param.zero2)
- printf(" /* zero tripped, %d %d %d */ ", param.zero0, param.zero1, param.zero2);
+ printf(" /* zero tripped, %u %u %u */ ", param.zero0, param.zero1, param.zero2);
}
static bool
return false;
}
+static bool
+is_op_attribute(unsigned op)
+{
+ switch (op) {
+ case midgard_op_ld_attr_16:
+ case midgard_op_ld_attr_32:
+ case midgard_op_ld_attr_32i:
+ case midgard_op_ld_attr_32u:
+ return true;
+ }
+
+ return false;
+}
+
static void
print_load_store_arg(uint8_t arg, unsigned index)
{
unsigned reg = REGISTER_LDST_BASE + sel.select;
char comp = components[sel.component];
- printf("r%d.%c", reg, comp);
+ printf("r%u.%c", reg, comp);
/* Only print a shift if it's non-zero. Shifts only make sense for the
* second index. For the first, we're not sure what it means yet */
if (index == 1) {
if (sel.shift)
- printf(" << %d", sel.shift);
+ printf(" << %u", sel.shift);
} else {
printf(" /* %X */", sel.shift);
}
}
+static void
+update_stats(signed *stat, unsigned address)
+{
+ if (*stat >= 0)
+ *stat = MAX2(*stat, address + 1);
+}
+
static void
print_load_store_instr(uint64_t data,
unsigned tabs)
print_ld_st_opcode(word->op);
- if (is_op_varying(word->op))
+ unsigned address = word->address;
+
+ if (is_op_varying(word->op)) {
print_varying_parameters(word);
- printf(" r%d", word->reg);
- print_mask_4(word->mask);
+ /* Do some analysis: check if direct cacess */
- int address = word->address;
+ if ((word->arg_2 == 0x1E) && midg_stats.varying_count >= 0)
+ update_stats(&midg_stats.varying_count, address);
+ else
+ midg_stats.varying_count = -16;
+ } else if (is_op_attribute(word->op)) {
+ if ((word->arg_2 == 0x1E) && midg_stats.attribute_count >= 0)
+ update_stats(&midg_stats.attribute_count, address);
+ else
+ midg_stats.attribute_count = -16;
+ }
+
+ printf(" r%u", word->reg + (OP_IS_STORE(word->op) ? 26 : 0));
+ print_mask_4(word->mask, false);
+
+ if (!OP_IS_STORE(word->op))
+ update_dest(word->reg);
bool is_ubo = OP_IS_UBO_READ(word->op);
address = (hi << 3) | lo;
}
- printf(", %d", address);
+ printf(", %u", address);
print_swizzle_vec4(word->swizzle, false, false);
printf(", ");
- if (is_ubo)
- printf("ubo%d", word->arg_1);
- else
+ if (is_ubo) {
+ printf("ubo%u", word->arg_1);
+ update_stats(&midg_stats.uniform_buffer_count, word->arg_1);
+ } else
print_load_store_arg(word->arg_1, 0);
printf(", ");
}
static void
-print_texture_reg(bool full, bool select, bool upper)
-{
- if (full)
- printf("r%d", REG_TEX_BASE + select);
- else
- printf("hr%d", (REG_TEX_BASE + select) * 2 + upper);
-
- if (full && upper)
- printf("// error: out full / upper mutually exclusive\n");
-
-}
-
-static void
-print_texture_reg_triple(unsigned triple)
-{
- bool full = triple & 1;
- bool select = triple & 2;
- bool upper = triple & 4;
-
- print_texture_reg(full, select, upper);
-}
-
-static void
-print_texture_reg_select(uint8_t u)
+print_texture_reg_select(uint8_t u, unsigned base)
{
midgard_tex_register_select sel;
memcpy(&sel, &u, sizeof(u));
if (!sel.full)
printf("h");
- printf("r%d", REG_TEX_BASE + sel.select);
+ printf("r%u", base + sel.select);
unsigned component = sel.component;
}
}
+static bool
+midgard_op_has_helpers(unsigned op, bool gather)
+{
+ if (gather)
+ return true;
+
+ switch (op) {
+ case TEXTURE_OP_NORMAL:
+ case TEXTURE_OP_DFDX:
+ case TEXTURE_OP_DFDY:
+ return true;
+ default:
+ return false;
+ }
+}
+
static void
print_texture_op(unsigned op, bool gather)
{
unsigned bottom = op & 0xF;
if (bottom != 0x2)
- printf("_unk%d", bottom);
+ printf("_unk%u", bottom);
printf(".%c", components[component]);
return;
#undef DEFINE_CASE
static void
-print_texture_word(uint32_t *word, unsigned tabs)
+print_texture_word(uint32_t *word, unsigned tabs, unsigned in_reg_base, unsigned out_reg_base)
{
midgard_texture_word *texture = (midgard_texture_word *) word;
+ midg_stats.helper_invocations |=
+ midgard_op_has_helpers(texture->op, texture->is_gather);
+
/* Broad category of texture operation in question */
print_texture_op(texture->op, texture->is_gather);
/* Output modifiers are always interpreted floatly */
print_outmod(texture->outmod, false);
- printf(" ");
-
- print_texture_reg(texture->out_full, texture->out_reg_select, texture->out_upper);
- print_mask_4(texture->mask);
+ printf(" %sr%u", texture->out_full ? "" : "h",
+ out_reg_base + texture->out_reg_select);
+ print_mask_4(texture->mask, texture->out_upper);
+ assert(!(texture->out_full && texture->out_upper));
printf(", ");
+ /* Depending on whether we read from textures directly or indirectly,
+ * we may be able to update our analysis */
+
if (texture->texture_register) {
printf("texture[");
- print_texture_reg_select(texture->texture_handle);
+ print_texture_reg_select(texture->texture_handle, in_reg_base);
printf("], ");
+
+ /* Indirect, tut tut */
+ midg_stats.texture_count = -16;
} else {
- printf("texture%d, ", texture->texture_handle);
+ printf("texture%u, ", texture->texture_handle);
+ update_stats(&midg_stats.texture_count, texture->texture_handle);
}
/* Print the type, GL style */
if (texture->sampler_register) {
printf("[");
- print_texture_reg_select(texture->sampler_handle);
+ print_texture_reg_select(texture->sampler_handle, in_reg_base);
printf("]");
+
+ midg_stats.sampler_count = -16;
} else {
- printf("%d", texture->sampler_handle);
+ printf("%u", texture->sampler_handle);
+ update_stats(&midg_stats.sampler_count, texture->sampler_handle);
}
print_swizzle_vec4(texture->swizzle, false, false);
- printf(", ");
+ printf(", %sr%u", texture->in_reg_full ? "" : "h", in_reg_base + texture->in_reg_select);
+ assert(!(texture->in_reg_full && texture->in_reg_upper));
+
+ /* TODO: integrate with swizzle */
+ if (texture->in_reg_upper)
+ printf("'");
- print_texture_reg(texture->in_reg_full, texture->in_reg_select, texture->in_reg_upper);
print_swizzle_vec4(texture->in_reg_swizzle, false, false);
/* There is *always* an offset attached. Of
if (texture->offset_register) {
printf(" + ");
- print_texture_reg_triple(texture->offset_x);
- /* The less questions you ask, the better. */
+ bool full = texture->offset & 1;
+ bool select = texture->offset & 2;
+ bool upper = texture->offset & 4;
- unsigned swizzle_lo, swizzle_hi;
- unsigned orig_y = texture->offset_y;
- unsigned orig_z = texture->offset_z;
+ printf("%sr%u", full ? "" : "h", in_reg_base + select);
+ assert(!(texture->out_full && texture->out_upper));
- memcpy(&swizzle_lo, &orig_y, sizeof(unsigned));
- memcpy(&swizzle_hi, &orig_z, sizeof(unsigned));
-
- /* Duplicate hi swizzle over */
- assert(swizzle_hi < 4);
- swizzle_hi = (swizzle_hi << 2) | swizzle_hi;
+ /* TODO: integrate with swizzle */
+ if (upper)
+ printf("'");
- unsigned swiz = (swizzle_lo << 4) | swizzle_hi;
- unsigned reversed = util_bitreverse(swiz) >> 24;
- print_swizzle_vec4(reversed, false, false);
+ print_swizzle_vec4(texture->offset >> 3, false, false);
printf(", ");
- } else if (texture->offset_x || texture->offset_y || texture->offset_z) {
+ } else if (texture->offset) {
/* Only select ops allow negative immediate offsets, verify */
- bool neg_x = texture->offset_x < 0;
- bool neg_y = texture->offset_y < 0;
- bool neg_z = texture->offset_z < 0;
+ signed offset_x = (texture->offset & 0xF);
+ signed offset_y = ((texture->offset >> 4) & 0xF);
+ signed offset_z = ((texture->offset >> 8) & 0xF);
+
+ bool neg_x = offset_x < 0;
+ bool neg_y = offset_y < 0;
+ bool neg_z = offset_z < 0;
bool any_neg = neg_x || neg_y || neg_z;
if (any_neg && texture->op != TEXTURE_OP_TEXEL_FETCH)
/* Regardless, just print the immediate offset */
- printf(" + <%d, %d, %d>, ",
- texture->offset_x,
- texture->offset_y,
- texture->offset_z);
+ printf(" + <%d, %d, %d>, ", offset_x, offset_y, offset_z);
} else {
printf(", ");
}
if (texture->lod_register) {
printf("lod %c ", lod_operand);
- print_texture_reg_select(texture->bias);
+ print_texture_reg_select(texture->bias, in_reg_base);
printf(", ");
if (texture->bias_int)
if (texture->bias_int)
printf(" /* bias_int = 0x%X */ ", texture->bias_int);
- printf("lod = %d, ", texture->bias);
+ printf("lod = %u, ", texture->bias);
} else if (texture->bias || texture->bias_int) {
signed bias_int = texture->bias_int;
float bias_frac = texture->bias / 256.0f;
}
struct midgard_disasm_stats
-disassemble_midgard(uint8_t *code, size_t size)
+disassemble_midgard(uint8_t *code, size_t size, unsigned gpu_id, gl_shader_stage stage)
{
uint32_t *words = (uint32_t *) code;
unsigned num_words = size / 4;
int tabs = 0;
- bool prefetch_flag = false;
+ bool branch_forward = false;
int last_next_tag = -1;
unsigned i = 0;
+ midg_tags = calloc(sizeof(midg_tags[0]), num_words);
+
/* Stats for shader-db */
memset(&midg_stats, 0, sizeof(midg_stats));
+ midg_ever_written = 0;
while (i < num_words) {
unsigned tag = words[i] & 0xF;
unsigned next_tag = (words[i] >> 4) & 0xF;
+ printf("\t%X -> %X\n", tag, next_tag);
unsigned num_quad_words = midgard_word_size[tag];
+ if (midg_tags[i] && midg_tags[i] != tag) {
+ printf("\t/* XXX: TAG ERROR branch, got ");
+ print_tag_short(tag);
+ printf(" expected ");
+ print_tag_short(midg_tags[i]);
+ printf(" */\n");
+ }
+
+ midg_tags[i] = tag;
+
/* Check the tag */
if (last_next_tag > 1) {
if (last_next_tag != tag) {
- printf("/* TAG ERROR got ");
+ printf("\t/* XXX: TAG ERROR sequence, got ");
print_tag_short(tag);
printf(" expected ");
print_tag_short(last_next_tag);
- printf(" */ ");
+ printf(" */\n");
}
} else {
/* TODO: Check ALU case */
last_next_tag = next_tag;
switch (midgard_word_types[tag]) {
- case midgard_word_type_texture:
- print_texture_word(&words[i], tabs);
+ case midgard_word_type_texture: {
+ bool interpipe_aliasing =
+ midgard_get_quirks(gpu_id) & MIDGARD_INTERPIPE_REG_ALIASING;
+
+ print_texture_word(&words[i], tabs,
+ interpipe_aliasing ? 0 : REG_TEX_BASE,
+ interpipe_aliasing ? REGISTER_LDST_BASE : REG_TEX_BASE);
break;
+ }
case midgard_word_type_load_store:
print_load_store_word(&words[i], tabs);
break;
case midgard_word_type_alu:
- print_alu_word(&words[i], num_quad_words, tabs);
+ branch_forward = print_alu_word(&words[i], num_quad_words, tabs, i + 4*num_quad_words);
/* Reset word static analysis state */
is_embedded_constant_half = false;
break;
}
- if (prefetch_flag && midgard_word_types[tag] == midgard_word_type_alu)
- break;
-
- printf("\n");
-
- unsigned next = (words[i] & 0xF0) >> 4;
+ /* We are parsing per bundle anyway. Add before we start
+ * breaking out so we don't miss the final bundle. */
- /* We are parsing per bundle anyway */
midg_stats.bundle_count++;
midg_stats.quadword_count += num_quad_words;
- /* Break based on instruction prefetch flag */
+ printf("\n");
- if (i < num_words && next == 1) {
- prefetch_flag = true;
+ unsigned next = (words[i] & 0xF0) >> 4;
- if (midgard_word_types[words[i] & 0xF] != midgard_word_type_alu)
- break;
- }
+ if (i < num_words && next == 1 && !branch_forward)
+ break;
i += 4 * num_quad_words;
}
+ /* We computed work_count as max_work_registers, so add one to get the
+ * count. If no work registers are written, you still have one work
+ * reported, which is exactly what the hardware expects */
+
+ midg_stats.work_count++;
+
return midg_stats;
}
projects / mesa.git / blobdiff