#include <stdint.h>
#include <stdbool.h>
-#include "panfrost-job.h"
#define MIDGARD_DBG_MSGS 0x0001
#define MIDGARD_DBG_SHADERS 0x0002
/* Packs a colour from fp16 to a native format */
midgard_op_pack_colour = 0x09,
+ /* Likewise packs from fp32 */
+ midgard_op_pack_colour_32 = 0x0A,
+
/* Unclear why this is on the L/S unit, but moves fp32 cube map
* coordinates in r27 to its cube map texture coordinate destination
* (e.g r29). */
midgard_op_ld_vary_32u = 0x9A,
midgard_op_ld_vary_32i = 0x9B,
- /* Old version of midgard_op_ld_color_buffer_u8_as_fp16, for T720 */
- midgard_op_ld_color_buffer_u8_as_fp16_old = 0x9D,
+ /* Old version of midgard_op_ld_color_buffer_as_fp16, for T720 */
+ midgard_op_ld_color_buffer_as_fp32_old = 0x9C,
+ midgard_op_ld_color_buffer_as_fp16_old = 0x9D,
+ midgard_op_ld_color_buffer_32u_old = 0x9E,
/* The distinction between these ops is the alignment requirement /
* accompanying shift. Thus, the offset to ld_ubo_int4 is in 16-byte
midgard_op_ld_ubo_int4 = 0xB0,
/* New-style blending ops. Works on T760/T860 */
- midgard_op_ld_color_buffer_u8_as_fp16 = 0xB9,
+ midgard_op_ld_color_buffer_as_fp32 = 0xB8,
+ midgard_op_ld_color_buffer_as_fp16 = 0xB9,
midgard_op_ld_color_buffer_32u = 0xBA,
midgard_op_st_char = 0xC0,
} midgard_load_store_op;
typedef enum {
+ midgard_interp_sample = 0,
midgard_interp_centroid = 1,
midgard_interp_default = 2
} midgard_interpolation;
/* Texture pipeline results are in r28-r29 */
#define REG_TEX_BASE 28
-/* Texture opcodes... maybe? */
-#define TEXTURE_OP_NORMAL 0x11 /* texture */
-#define TEXTURE_OP_LOD 0x12 /* textureLod */
-#define TEXTURE_OP_TEXEL_FETCH 0x14 /* texelFetch */
-
-/* Implements barrier() */
-#define TEXTURE_OP_BARRIER 0x0B
-
-/* Computes horizontal and vertical derivatives respectively. Use with a float
- * sampler and a "2D" texture. Leave texture/sampler IDs as zero; they ought
- * to be ignored. Only works for fp32 on 64-bit at a time, so derivatives of a
- * vec4 require 2 texture ops. For some reason, the blob computes both X and Y
- * derivatives at the same time and just throws out whichever is unused; it's
- * not known if this is a quirk of the hardware or just of the blob. */
-
-#define TEXTURE_OP_DFDX 0x0D
-#define TEXTURE_OP_DFDY 0x1D
+enum mali_texture_op {
+ TEXTURE_OP_NORMAL = 1, /* texture */
+ TEXTURE_OP_LOD = 2, /* textureLod */
+ TEXTURE_OP_TEXEL_FETCH = 4,
+ TEXTURE_OP_BARRIER = 11,
+ TEXTURE_OP_DERIVATIVE = 13
+};
enum mali_sampler_type {
MALI_SAMPLER_UNK = 0x0,
MALI_SAMPLER_SIGNED = 0x3, /* isampler */
};
+/* Texture modes */
+enum mali_texture_mode {
+ TEXTURE_NORMAL = 1,
+ TEXTURE_SHADOW = 5,
+ TEXTURE_GATHER_SHADOW = 6,
+ TEXTURE_GATHER_X = 8,
+ TEXTURE_GATHER_Y = 9,
+ TEXTURE_GATHER_Z = 10,
+ TEXTURE_GATHER_W = 11,
+};
+
+enum mali_derivative_mode {
+ TEXTURE_DFDX = 0,
+ TEXTURE_DFDY = 1,
+};
+
typedef struct
__attribute__((__packed__))
{
unsigned type : 4;
unsigned next_type : 4;
- unsigned op : 6;
- unsigned shadow : 1;
- unsigned is_gather : 1;
+ enum mali_texture_op op : 4;
+ unsigned mode : 4;
/* A little obscure, but last is set for the last texture operation in
* a shader. cont appears to just be last's opposite (?). Yeah, I know,
unsigned cont : 1;
unsigned last : 1;
- enum mali_texture_type format : 2;
+ unsigned format : 2;
/* Are sampler_handle/texture_handler respectively set by registers? If
* true, the lower 8-bits of the respective field is a register word.
unsigned mask : 4;
- /* Intriguingly, textures can take an outmod just like textures. Int
+ /* Intriguingly, textures can take an outmod just like alu ops. Int
* outmods are not supported as far as I can tell, so this is only
* meaningful for float samplers */
midgard_outmod_float outmod : 2;
unsigned swizzle : 8;
- /* For barriers, control barriers are implied regardless, but these
- * bits also enable memory barriers of various types. For regular
- * textures, these bits are not yet understood. */
- unsigned barrier_buffer : 1;
- unsigned barrier_shared : 1;
- unsigned barrier_stack : 1;
+ /* These indicate how many bundles after this texture op may be
+ * executed in parallel with this op. We may execute only ALU and
+ * ld/st in parallel (not other textures), and obviously there cannot
+ * be any dependency (the blob appears to forbid even accessing other
+ * channels of a given texture register). */
- unsigned unknown4 : 9;
+ unsigned out_of_order : 2;
+ unsigned unknown4 : 10;
/* In immediate mode, each offset field is an immediate range [0, 7].
*
- * In register mode, offset_x becomes a register full / select / upper
+ * In register mode, offset_x becomes a register (full, select, upper)
* triplet followed by a vec3 swizzle is splattered across
* offset_y/offset_z in a genuinely bizarre way.
*
unsigned zero2 : 14;
unsigned zero3 : 24;
- unsigned buffer : 1;
- unsigned shared : 1;
- unsigned stack : 1;
- unsigned zero4 : 5;
+ unsigned out_of_order : 4;
+ unsigned zero4 : 4;
uint64_t zero5;
} midgard_texture_barrier_word;
}
midgard_constants;
+enum midgard_roundmode {
+ MIDGARD_RTE = 0x0, /* round to even */
+ MIDGARD_RTZ = 0x1, /* round to zero */
+ MIDGARD_RTN = 0x2, /* round to negative */
+ MIDGARD_RTP = 0x3, /* round to positive */
+};
+
#endif