pan/midgard: Add units for more instructions

[mesa.git] / src / panfrost / midgard / midgard_compile.c

diff --git a/src/panfrost/midgard/midgard_compile.c b/src/panfrost/midgard/midgard_compile.c
index dbc5a338017ce980c61416265b7cd9afc908f249..1efc5538b42b2dbf980b4afaf8bbf2db77ac075c 100644 (file)
--- a/src/panfrost/midgard/midgard_compile.c
+++ b/src/panfrost/midgard/midgard_compile.c
@@ -224,7 +224,11 @@ midgard_create_branch_extended( midgard_condition cond,
                                 unsigned dest_tag,
                                 signed quadword_offset)
 {
-        /* For unclear reasons, the condition code is repeated 8 times */
+        /* The condition code is actually a LUT describing a function to
+         * combine multiple condition codes. However, we only support a single
+         * condition code at the moment, so we just duplicate over a bunch of
+         * times. */
+
         uint16_t duplicated_cond =
                 (cond << 14) |
                 (cond << 12) |
@@ -293,17 +297,6 @@ midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr *instr)
         }
 }
 
-static unsigned
-nir_dest_index(compiler_context *ctx, nir_dest *dst)
-{
-        if (dst->is_ssa)
-                return (dst->ssa.index << 1) | 0;
-        else {
-                assert(!dst->reg.indirect);
-                return (dst->reg.reg->index << 1) | IS_REG;
-        }
-}
-
 static int sysval_for_instr(compiler_context *ctx, nir_instr *instr,
                             unsigned *dest)
 {
@@ -547,23 +540,6 @@ emit_explicit_constant(compiler_context *ctx, unsigned node, unsigned to)
         }
 }
 
-static unsigned
-nir_src_index(compiler_context *ctx, nir_src *src)
-{
-        if (src->is_ssa)
-                return (src->ssa->index << 1) | 0;
-        else {
-                assert(!src->reg.indirect);
-                return (src->reg.reg->index << 1) | IS_REG;
-        }
-}
-
-static unsigned
-nir_alu_src_index(compiler_context *ctx, nir_alu_src *src)
-{
-        return nir_src_index(ctx, &src->src);
-}
-
 static bool
 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
 {
@@ -742,6 +718,14 @@ reg_mode_for_nir(nir_alu_instr *instr)
 static void
 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
 {
+        /* Derivatives end up emitted on the texture pipe, not the ALUs. This
+         * is handled elsewhere */
+
+        if (instr->op == nir_op_fddx || instr->op == nir_op_fddy) {
+                midgard_emit_derivatives(ctx, instr);
+                return;
+        }
+
         bool is_ssa = instr->dest.dest.is_ssa;
 
         unsigned dest = nir_dest_index(ctx, &instr->dest.dest);
@@ -1897,8 +1881,7 @@ embedded_to_inline_constant(compiler_context *ctx)
 
                         /* We don't know how to handle these with a constant */
 
-                        bool is_int = midgard_is_integer_op(ins->alu.op);
-                        if (mir_nontrivial_raw_mod(*src, is_int) || src->half || src->rep_low || src->rep_high) {
+                        if (mir_nontrivial_source2_mod_simple(ins) || src->rep_low || src->rep_high) {
                                 DBG("Bailing inline constant...\n");
                                 continue;
                         }
@@ -2375,6 +2358,7 @@ midgard_compile_shader_nir(struct midgard_screen *screen, nir_shader *nir, midga
 
         mir_foreach_block(ctx, block) {
                 midgard_lower_invert(ctx, block);
+                midgard_lower_derivatives(ctx, block);
         }
 
         /* Nested control-flow can result in dead branches at the end of the