#include "midgard_ops.h"
#include "helpers.h"
#include "compiler.h"
+#include "midgard_quirks.h"
#include "disassemble.h"
do { if (midgard_debug & MIDGARD_DBG_MSGS) \
fprintf(stderr, "%s:%d: "fmt, \
__FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
-
-static bool
-midgard_is_branch_unit(unsigned unit)
+static midgard_block *
+create_empty_block(compiler_context *ctx)
{
- return (unit == ALU_ENAB_BRANCH) || (unit == ALU_ENAB_BR_COMPACT);
+ midgard_block *blk = rzalloc(ctx, midgard_block);
+
+ blk->predecessors = _mesa_set_create(blk,
+ _mesa_hash_pointer,
+ _mesa_key_pointer_equal);
+
+ blk->source_id = ctx->block_source_count++;
+
+ return blk;
}
static void
block->successors[block->nr_successors++] = successor;
assert(block->nr_successors <= ARRAY_SIZE(block->successors));
+
+ /* Note the predecessor in the other direction */
+ _mesa_set_add(successor->predecessors, block);
+}
+
+static void
+schedule_barrier(compiler_context *ctx)
+{
+ midgard_block *temp = ctx->after_block;
+ ctx->after_block = create_empty_block(ctx);
+ ctx->block_count++;
+ list_addtail(&ctx->after_block->link, &ctx->blocks);
+ list_inithead(&ctx->after_block->instructions);
+ midgard_block_add_successor(ctx->current_block, ctx->after_block);
+ ctx->current_block = ctx->after_block;
+ ctx->after_block = temp;
}
/* Helpers to generate midgard_instruction's using macro magic, since every
midgard_instruction i = { \
.type = TAG_LOAD_STORE_4, \
.mask = 0xF, \
- .ssa_args = { \
- .dest = -1, \
- .src = { -1, -1, -1 }, \
- }, \
+ .dest = ~0, \
+ .src = { ~0, ~0, ~0, ~0 }, \
+ .swizzle = SWIZZLE_IDENTITY_4, \
.load_store = { \
.op = midgard_op_##name, \
- .swizzle = SWIZZLE_XYZW, \
.address = address \
} \
}; \
\
if (store) \
- i.ssa_args.src[0] = ssa; \
+ i.src[0] = ssa; \
else \
- i.ssa_args.dest = ssa; \
+ i.dest = ssa; \
\
return i; \
}
vector_alu_modifiers(nir_alu_src *src, bool is_int, unsigned broadcast_count,
bool half, bool sext)
{
- if (!src) return blank_alu_src;
-
- /* Figure out how many components there are so we can adjust the
- * swizzle. Specifically we want to broadcast the last channel so
- * things like ball2/3 work
+ /* Figure out how many components there are so we can adjust.
+ * Specifically we want to broadcast the last channel so things like
+ * ball2/3 work.
*/
- if (broadcast_count) {
+ if (broadcast_count && src) {
uint8_t last_component = src->swizzle[broadcast_count - 1];
for (unsigned c = broadcast_count; c < NIR_MAX_VEC_COMPONENTS; ++c) {
midgard_vector_alu_src alu_src = {
.rep_low = 0,
.rep_high = 0,
- .half = half,
- .swizzle = SWIZZLE_FROM_ARRAY(src->swizzle)
+ .half = half
};
if (is_int) {
}
/* These should have been lowered away */
- assert(!(src->abs || src->negate));
+ if (src)
+ assert(!(src->abs || src->negate));
} else {
- alu_src.mod = (src->abs << 0) | (src->negate << 1);
+ if (src)
+ alu_src.mod = (src->abs << 0) | (src->negate << 1);
}
return alu_src;
M_LOAD(ld_ubo_int4);
M_LOAD(ld_int4);
M_STORE(st_int4);
-M_LOAD(ld_color_buffer_8);
+M_LOAD(ld_color_buffer_32u);
//M_STORE(st_vary_16);
M_STORE(st_vary_32);
-M_LOAD(st_cubemap_coords);
+M_LOAD(ld_cubemap_coords);
M_LOAD(ld_compute_id);
-
-static midgard_instruction
-v_alu_br_compact_cond(midgard_jmp_writeout_op op, unsigned tag, signed offset, unsigned cond)
-{
- midgard_branch_cond branch = {
- .op = op,
- .dest_tag = tag,
- .offset = offset,
- .cond = cond
- };
-
- uint16_t compact;
- memcpy(&compact, &branch, sizeof(branch));
-
- midgard_instruction ins = {
- .type = TAG_ALU_4,
- .unit = ALU_ENAB_BR_COMPACT,
- .prepacked_branch = true,
- .compact_branch = true,
- .br_compact = compact,
- .ssa_args = {
- .dest = -1,
- .src = { -1, -1, -1 },
- }
- };
-
- if (op == midgard_jmp_writeout_op_writeout)
- ins.writeout = true;
-
- return ins;
-}
+M_LOAD(pack_colour);
static midgard_instruction
v_branch(bool conditional, bool invert)
.conditional = conditional,
.invert_conditional = invert
},
- .ssa_args = {
- .dest = -1,
- .src = { -1, -1, -1 },
- }
+ .dest = ~0,
+ .src = { ~0, ~0, ~0, ~0 },
};
return ins;
return PAN_SYSVAL(SSBO, uindex);
}
+static int
+midgard_sysval_for_sampler(nir_intrinsic_instr *instr)
+{
+ /* TODO: indirect samplers !!! */
+ nir_src index = instr->src[0];
+ assert(nir_src_is_const(index));
+ uint32_t uindex = nir_src_as_uint(index);
+
+ return PAN_SYSVAL(SAMPLER, uindex);
+}
+
static int
midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr *instr)
{
case nir_intrinsic_load_ssbo:
case nir_intrinsic_store_ssbo:
return midgard_sysval_for_ssbo(instr);
+ case nir_intrinsic_load_sampler_lod_parameters_pan:
+ return midgard_sysval_for_sampler(instr);
default:
- return -1;
+ return ~0;
}
}
/* Flushes undefined values to zero */
static void
-optimise_nir(nir_shader *nir)
+optimise_nir(nir_shader *nir, unsigned quirks)
{
bool progress;
unsigned lower_flrp =
(nir->options->lower_flrp64 ? 64 : 0);
NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
- NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
- NIR_PASS(progress, nir, nir_lower_idiv);
-
- nir_lower_tex_options lower_tex_1st_pass_options = {
- .lower_rect = true,
- .lower_txp = ~0
- };
+ NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
- nir_lower_tex_options lower_tex_2nd_pass_options = {
+ nir_lower_tex_options lower_tex_options = {
.lower_txs_lod = true,
+ .lower_txp = ~0,
+ .lower_tex_without_implicit_lod =
+ (quirks & MIDGARD_EXPLICIT_LOD),
+
+ /* TODO: we have native gradient.. */
+ .lower_txd = true,
};
- NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_1st_pass_options);
- NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_2nd_pass_options);
+ NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
+
+ /* Must lower fdot2 after tex is lowered */
+ NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
+
+ /* T720 is broken. */
+
+ if (quirks & MIDGARD_BROKEN_LOD)
+ NIR_PASS_V(nir, midgard_nir_lod_errata);
do {
progress = false;
NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
NIR_PASS(progress, nir, nir_copy_prop);
+ NIR_PASS(progress, nir, nir_opt_remove_phis);
NIR_PASS(progress, nir, nir_opt_dce);
NIR_PASS(progress, nir, nir_opt_dead_cf);
NIR_PASS(progress, nir, nir_opt_cse);
nir_ssa_def def = instr->def;
float *v = rzalloc_array(NULL, float, 4);
- nir_const_load_to_arr(v, instr, f32);
+ nir_const_value_to_array(v, instr->value, instr->def.num_components, f32);
/* Shifted for SSA, +1 for off-by-one */
_mesa_hash_table_u64_insert(ctx->ssa_constants, (def.index << 1) + 1, v);
void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, node + 1);
if (constant_value) {
- midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, to);
+ midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to);
attach_constants(ctx, &ins, constant_value, node + 1);
emit_mir_instruction(ctx, ins);
}
return false;
}
-/* Midgard puts scalar conditionals in r31.w; move an arbitrary source (the
- * output of a conditional test) into that register */
-
-static void
-emit_condition(compiler_context *ctx, nir_src *src, bool for_branch, unsigned component)
-{
- int condition = nir_src_index(ctx, src);
-
- /* Source to swizzle the desired component into w */
-
- const midgard_vector_alu_src alu_src = {
- .swizzle = SWIZZLE(component, component, component, component),
- };
-
- /* There is no boolean move instruction. Instead, we simulate a move by
- * ANDing the condition with itself to get it into r31.w */
-
- midgard_instruction ins = {
- .type = TAG_ALU_4,
-
- /* We need to set the conditional as close as possible */
- .precede_break = true,
- .unit = for_branch ? UNIT_SMUL : UNIT_SADD,
- .mask = 1 << COMPONENT_W,
-
- .ssa_args = {
- .src = { condition, condition, -1 },
- .dest = SSA_FIXED_REGISTER(31),
- },
-
- .alu = {
- .op = midgard_alu_op_iand,
- .outmod = midgard_outmod_int_wrap,
- .reg_mode = midgard_reg_mode_32,
- .dest_override = midgard_dest_override_none,
- .src1 = vector_alu_srco_unsigned(alu_src),
- .src2 = vector_alu_srco_unsigned(alu_src)
- },
- };
-
- emit_mir_instruction(ctx, ins);
-}
-
-/* Or, for mixed conditions (with csel_v), here's a vector version using all of
- * r31 instead */
-
-static void
-emit_condition_mixed(compiler_context *ctx, nir_alu_src *src, unsigned nr_comp)
-{
- int condition = nir_src_index(ctx, &src->src);
-
- /* Source to swizzle the desired component into w */
-
- const midgard_vector_alu_src alu_src = {
- .swizzle = SWIZZLE_FROM_ARRAY(src->swizzle),
- };
-
- /* There is no boolean move instruction. Instead, we simulate a move by
- * ANDing the condition with itself to get it into r31.w */
-
- midgard_instruction ins = {
- .type = TAG_ALU_4,
- .precede_break = true,
- .mask = mask_of(nr_comp),
- .ssa_args = {
- .src = { condition, condition, -1 },
- .dest = SSA_FIXED_REGISTER(31),
- },
- .alu = {
- .op = midgard_alu_op_iand,
- .outmod = midgard_outmod_int_wrap,
- .reg_mode = midgard_reg_mode_32,
- .dest_override = midgard_dest_override_none,
- .src1 = vector_alu_srco_unsigned(alu_src),
- .src2 = vector_alu_srco_unsigned(alu_src)
- },
- };
-
- emit_mir_instruction(ctx, ins);
-}
-
#define ALU_CASE(nir, _op) \
case nir_op_##nir: \
op = midgard_alu_op_##_op; \
case nir_op_i2i8:
case nir_op_i2i16:
case nir_op_i2i32:
+ case nir_op_i2i64:
/* If we end up upscale, we'll need a sign-extend on the
* operand (the second argument) */
sext_2 = true;
+ /* fallthrough */
case nir_op_u2u8:
case nir_op_u2u16:
- case nir_op_u2u32: {
+ case nir_op_u2u32:
+ case nir_op_u2u64: {
op = midgard_alu_op_imov;
if (dst_bitsize == (src_bitsize * 2)) {
bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
op = mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel;
- /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
- nr_inputs = 2;
-
- /* Emit the condition into r31 */
-
- if (mixed)
- emit_condition_mixed(ctx, &instr->src[0], nr_components);
- else
- emit_condition(ctx, &instr->src[0].src, false, instr->src[0].swizzle[0]);
-
/* The condition is the first argument; move the other
* arguments up one to be a binary instruction for
- * Midgard */
+ * Midgard with the condition last */
+
+ nir_alu_src temp = instr->src[2];
+
+ instr->src[2] = instr->src[0];
+ instr->src[0] = instr->src[1];
+ instr->src[1] = temp;
- memmove(instr->src, instr->src + 1, 2 * sizeof(nir_alu_src));
break;
}
* needs it, or else we may segfault. */
unsigned src0 = nir_alu_src_index(ctx, &instr->src[0]);
- unsigned src1 = nr_inputs == 2 ? nir_alu_src_index(ctx, &instr->src[1]) : SSA_UNUSED_0;
+ unsigned src1 = nr_inputs >= 2 ? nir_alu_src_index(ctx, &instr->src[1]) : ~0;
+ unsigned src2 = nr_inputs == 3 ? nir_alu_src_index(ctx, &instr->src[2]) : ~0;
+ assert(nr_inputs <= 3);
/* Rather than use the instruction generation helpers, we do it
* ourselves here to avoid the mess */
midgard_instruction ins = {
.type = TAG_ALU_4,
- .ssa_args = {
- .src = {
- quirk_flipped_r24 ? SSA_UNUSED_1 : src0,
- quirk_flipped_r24 ? src0 : src1,
- -1
- },
- .dest = dest,
- }
+ .src = {
+ quirk_flipped_r24 ? ~0 : src0,
+ quirk_flipped_r24 ? src0 : src1,
+ src2,
+ ~0
+ },
+ .dest = dest,
};
- nir_alu_src *nirmods[2] = { NULL };
+ nir_alu_src *nirmods[3] = { NULL };
- if (nr_inputs == 2) {
+ if (nr_inputs >= 2) {
nirmods[0] = &instr->src[0];
nirmods[1] = &instr->src[1];
} else if (nr_inputs == 1) {
assert(0);
}
+ if (nr_inputs == 3)
+ nirmods[2] = &instr->src[2];
+
/* These were lowered to a move, so apply the corresponding mod */
if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
if (!is_ssa)
ins.mask &= instr->dest.write_mask;
+ for (unsigned m = 0; m < 3; ++m) {
+ if (!nirmods[m])
+ continue;
+
+ for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c)
+ ins.swizzle[m][c] = nirmods[m]->swizzle[c];
+
+ /* Replicate. TODO: remove when vec16 lands */
+ for (unsigned c = NIR_MAX_VEC_COMPONENTS; c < MIR_VEC_COMPONENTS; ++c)
+ ins.swizzle[m][c] = nirmods[m]->swizzle[NIR_MAX_VEC_COMPONENTS - 1];
+ }
+
+ if (nr_inputs == 3) {
+ /* Conditions can't have mods */
+ assert(!nirmods[2]->abs);
+ assert(!nirmods[2]->negate);
+ }
+
ins.alu = alu;
/* Late fixup for emulated instructions */
* inline, since we're 32-bit, not 16-bit like the inline
* constants) */
- ins.ssa_args.inline_constant = false;
- ins.ssa_args.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
+ ins.has_inline_constant = false;
+ ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
ins.has_constants = true;
if (instr->op == nir_op_b2f32) {
- ins.constants[0] = 1.0f;
+ float f = 1.0f;
+ memcpy(&ins.constants, &f, sizeof(float));
} else {
- /* Type pun it into place */
- uint32_t one = 0x1;
- memcpy(&ins.constants[0], &one, sizeof(uint32_t));
+ ins.constants[0] = 1;
}
- ins.alu.src2 = vector_alu_srco_unsigned(blank_alu_src_xxxx);
+
+ for (unsigned c = 0; c < 16; ++c)
+ ins.swizzle[1][c] = 0;
} else if (nr_inputs == 1 && !quirk_flipped_r24) {
/* Lots of instructions need a 0 plonked in */
- ins.ssa_args.inline_constant = false;
- ins.ssa_args.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
+ ins.has_inline_constant = false;
+ ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
ins.has_constants = true;
- ins.constants[0] = 0.0f;
- ins.alu.src2 = vector_alu_srco_unsigned(blank_alu_src_xxxx);
+ ins.constants[0] = 0;
+
+ for (unsigned c = 0; c < 16; ++c)
+ ins.swizzle[1][c] = 0;
} else if (instr->op == nir_op_inot) {
ins.invert = true;
}
* instructions can only operate as if they were scalars. Lower
* them here by changing the component. */
- uint8_t original_swizzle[4];
- memcpy(original_swizzle, nirmods[0]->swizzle, sizeof(nirmods[0]->swizzle));
unsigned orig_mask = ins.mask;
for (int i = 0; i < nr_components; ++i) {
if (!ins.mask)
continue;
- for (int j = 0; j < 4; ++j)
- nirmods[0]->swizzle[j] = original_swizzle[i]; /* Pull from the correct component */
+ for (unsigned j = 0; j < MIR_VEC_COMPONENTS; ++j)
+ ins.swizzle[0][j] = nirmods[0]->swizzle[i]; /* Pull from the correct component */
- ins.alu.src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int, broadcast_swizzle, half_1, false));
emit_mir_instruction(ctx, ins);
}
} else {
#undef ALU_CASE
-static unsigned
-mir_mask_for_intr(nir_instr *instr, bool is_read)
+static void
+mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
{
nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
+ unsigned nir_mask = 0;
+ unsigned dsize = 0;
- if (is_read)
- return mask_of(nir_intrinsic_dest_components(intr));
- else
- return nir_intrinsic_write_mask(intr);
+ if (is_read) {
+ nir_mask = mask_of(nir_intrinsic_dest_components(intr));
+ dsize = nir_dest_bit_size(intr->dest);
+ } else {
+ nir_mask = nir_intrinsic_write_mask(intr);
+ dsize = 32;
+ }
+
+ /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
+ unsigned bytemask = mir_to_bytemask(mir_mode_for_destsize(dsize), nir_mask);
+ mir_set_bytemask(ins, bytemask);
+
+ if (dsize == 64)
+ ins->load_64 = true;
}
/* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
* optimized) versions of UBO #0 */
-midgard_instruction *
+static midgard_instruction *
emit_ubo_read(
compiler_context *ctx,
nir_instr *instr,
unsigned dest,
unsigned offset,
nir_src *indirect_offset,
+ unsigned indirect_shift,
unsigned index)
{
/* TODO: half-floats */
- midgard_instruction ins = m_ld_ubo_int4(dest, offset);
+ midgard_instruction ins = m_ld_ubo_int4(dest, 0);
+ ins.constants[0] = offset;
- /* TODO: Don't split */
- ins.load_store.varying_parameters = (offset & 7) << 7;
- ins.load_store.address = offset >> 3;
- ins.mask = mir_mask_for_intr(instr, true);
+ if (instr->type == nir_instr_type_intrinsic)
+ mir_set_intr_mask(instr, &ins, true);
if (indirect_offset) {
- ins.ssa_args.src[1] = nir_src_index(ctx, indirect_offset);
- ins.load_store.arg_2 = 0x80;
+ ins.src[2] = nir_src_index(ctx, indirect_offset);
+ ins.load_store.arg_2 = (indirect_shift << 5);
} else {
ins.load_store.arg_2 = 0x1E;
}
unsigned addr = make_compiler_temp(ctx);
emit_sysval_read(ctx, instr, addr, 2);
- /* The source array is a bit of a leaky abstraction for SSBOs.
- * Nevertheless, for loads:
- *
- * src[0] = arg_1
- * src[1] = arg_2
- * src[2] = unused
- *
- * Whereas for stores:
+ /* The source array:
*
- * src[0] = value
+ * src[0] = store ? value : unused
* src[1] = arg_1
* src[2] = arg_2
*
* arg_2 = the offset.
*/
- ins.ssa_args.src[is_read ? 0 : 1] = addr;
+ ins.src[1] = addr;
/* TODO: What is this? It looks superficially like a shift << 5, but
- * arg_1 doesn't take a shift Should it be E0 or A0? */
- if (indirect_offset)
- ins.load_store.arg_1 |= 0xE0;
+ * arg_1 doesn't take a shift Should it be E0 or A0? We also need the
+ * indirect offset. */
- /* We also need to emit the indirect offset */
-
- if (indirect_offset)
- ins.ssa_args.src[is_read ? 1 : 2] = nir_src_index(ctx, indirect_offset);
- else
+ if (indirect_offset) {
+ ins.load_store.arg_1 |= 0xE0;
+ ins.src[2] = nir_src_index(ctx, indirect_offset);
+ } else {
ins.load_store.arg_2 = 0x7E;
+ }
/* TODO: Bounds check */
ins.load_store.varying_parameters = (offset & 0x1FF) << 1;
ins.load_store.address = (offset >> 9);
- ins.mask = mir_mask_for_intr(instr, is_read);
+ mir_set_intr_mask(instr, &ins, is_read);
emit_mir_instruction(ctx, ins);
}
compiler_context *ctx,
unsigned dest, unsigned offset,
unsigned nr_comp, unsigned component,
- nir_src *indirect_offset, nir_alu_type type)
+ nir_src *indirect_offset, nir_alu_type type, bool flat)
{
/* XXX: Half-floats? */
/* TODO: swizzle, mask */
midgard_instruction ins = m_ld_vary_32(dest, offset);
ins.mask = mask_of(nr_comp);
- ins.load_store.swizzle = SWIZZLE_XYZW >> (2 * component);
+
+ for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
+ ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
midgard_varying_parameter p = {
.is_varying = 1,
.interpolation = midgard_interp_default,
- .flat = /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
+ .flat = flat,
};
unsigned u;
ins.load_store.varying_parameters = u;
if (indirect_offset)
- ins.ssa_args.src[1] = nir_src_index(ctx, indirect_offset);
+ ins.src[2] = nir_src_index(ctx, indirect_offset);
else
ins.load_store.arg_2 = 0x1E;
emit_mir_instruction(ctx, ins);
}
+static void
+emit_attr_read(
+ compiler_context *ctx,
+ unsigned dest, unsigned offset,
+ unsigned nr_comp, nir_alu_type t)
+{
+ midgard_instruction ins = m_ld_attr_32(dest, offset);
+ ins.load_store.arg_1 = 0x1E;
+ ins.load_store.arg_2 = 0x1E;
+ ins.mask = mask_of(nr_comp);
+
+ /* Use the type appropriate load */
+ switch (t) {
+ case nir_type_uint:
+ case nir_type_bool:
+ ins.load_store.op = midgard_op_ld_attr_32u;
+ break;
+ case nir_type_int:
+ ins.load_store.op = midgard_op_ld_attr_32i;
+ break;
+ case nir_type_float:
+ ins.load_store.op = midgard_op_ld_attr_32;
+ break;
+ default:
+ unreachable("Attempted to load unknown type");
+ break;
+ }
+
+ emit_mir_instruction(ctx, ins);
+}
+
void
emit_sysval_read(compiler_context *ctx, nir_instr *instr, signed dest_override,
unsigned nr_components)
/* Emit the read itself -- this is never indirect */
midgard_instruction *ins =
- emit_ubo_read(ctx, instr, dest, uniform, NULL, 0);
+ emit_ubo_read(ctx, instr, dest, uniform * 16, NULL, 0, 0);
ins->mask = mask_of(nr_components);
}
}
}
-/* Emit store for a fragment shader, which is encoded via a fancy branch. TODO:
- * Handle MRT here */
-
static void
emit_fragment_store(compiler_context *ctx, unsigned src, unsigned rt)
{
- /* First, move in whatever we're outputting */
- midgard_instruction move = v_mov(src, blank_alu_src, SSA_FIXED_REGISTER(0));
- if (rt != 0) {
- /* Force a tight schedule. TODO: Make the scheduler MRT aware */
- move.unit = UNIT_VMUL;
- move.precede_break = true;
- move.dont_eliminate = true;
- }
-
- emit_mir_instruction(ctx, move);
+ emit_explicit_constant(ctx, src, src);
- /* If we're doing MRT, we need to specify the render target */
-
- midgard_instruction rt_move = {
- .ssa_args = {
- .dest = -1
- }
- };
-
- if (rt != 0) {
- /* We'll write to r1.z */
- rt_move = v_mov(-1, blank_alu_src, SSA_FIXED_REGISTER(1));
- rt_move.mask = 1 << COMPONENT_Z;
- rt_move.unit = UNIT_SADD;
-
- /* r1.z = (rt * 0x100) */
- rt_move.ssa_args.inline_constant = true;
- rt_move.inline_constant = (rt * 0x100);
+ struct midgard_instruction ins =
+ v_branch(false, false);
- /* r1 */
- ctx->work_registers = MAX2(ctx->work_registers, 1);
+ ins.writeout = true;
- /* Do the write */
- emit_mir_instruction(ctx, rt_move);
- }
+ /* Add dependencies */
+ ins.src[0] = src;
+ ins.constants[0] = rt * 0x100;
- /* Next, generate the branch. For R render targets in the writeout, the
- * i'th render target jumps to pseudo-offset [2(R-1) + i] */
+ /* Emit the branch */
+ midgard_instruction *br = emit_mir_instruction(ctx, ins);
+ schedule_barrier(ctx);
- unsigned offset = (2 * (ctx->nir->num_outputs - 1)) + rt;
+ assert(rt < ARRAY_SIZE(ctx->writeout_branch));
+ assert(!ctx->writeout_branch[rt]);
+ ctx->writeout_branch[rt] = br;
- struct midgard_instruction ins =
- v_alu_br_compact_cond(midgard_jmp_writeout_op_writeout, TAG_ALU_4, offset, midgard_condition_always);
+ /* Push our current location = current block count - 1 = where we'll
+ * jump to. Maybe a bit too clever for my own good */
- /* Add dependencies */
- ins.ssa_args.src[0] = move.ssa_args.dest;
- ins.ssa_args.src[1] = rt_move.ssa_args.dest;
-
- /* Emit the branch */
- emit_mir_instruction(ctx, ins);
+ br->branch.target_block = ctx->block_count - 1;
}
static void
ins.load_store.arg_1 = compute_builtin_arg(instr->intrinsic);
emit_mir_instruction(ctx, ins);
}
+
+static unsigned
+vertex_builtin_arg(nir_op op)
+{
+ switch (op) {
+ case nir_intrinsic_load_vertex_id:
+ return PAN_VERTEX_ID;
+ case nir_intrinsic_load_instance_id:
+ return PAN_INSTANCE_ID;
+ default:
+ unreachable("Invalid vertex builtin");
+ }
+}
+
+static void
+emit_vertex_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
+{
+ unsigned reg = nir_dest_index(ctx, &instr->dest);
+ emit_attr_read(ctx, reg, vertex_builtin_arg(instr->intrinsic), 1, nir_type_int);
+}
+
static void
emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
{
switch (instr->intrinsic) {
case nir_intrinsic_discard_if:
- emit_condition(ctx, &instr->src[0], true, COMPONENT_X);
-
- /* fallthrough */
-
case nir_intrinsic_discard: {
bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
struct midgard_instruction discard = v_branch(conditional, false);
discard.branch.target_type = TARGET_DISCARD;
+
+ if (conditional)
+ discard.src[0] = nir_src_index(ctx, &instr->src[0]);
+
emit_mir_instruction(ctx, discard);
+ schedule_barrier(ctx);
+
break;
}
case nir_intrinsic_load_uniform:
case nir_intrinsic_load_ubo:
case nir_intrinsic_load_ssbo:
- case nir_intrinsic_load_input: {
+ case nir_intrinsic_load_input:
+ case nir_intrinsic_load_interpolated_input: {
bool is_uniform = instr->intrinsic == nir_intrinsic_load_uniform;
bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo;
bool is_ssbo = instr->intrinsic == nir_intrinsic_load_ssbo;
+ bool is_flat = instr->intrinsic == nir_intrinsic_load_input;
+ bool is_interp = instr->intrinsic == nir_intrinsic_load_interpolated_input;
/* Get the base type of the intrinsic */
/* TODO: Infer type? Does it matter? */
nir_alu_type t =
- (is_ubo || is_ssbo) ? nir_type_uint : nir_intrinsic_type(instr);
+ (is_ubo || is_ssbo) ? nir_type_uint :
+ (is_interp) ? nir_type_float :
+ nir_intrinsic_type(instr);
+
t = nir_alu_type_get_base_type(t);
if (!(is_ubo || is_ssbo)) {
offset += nir_src_as_uint(*src_offset);
/* We may need to apply a fractional offset */
- int component = instr->intrinsic == nir_intrinsic_load_input ?
+ int component = (is_flat || is_interp) ?
nir_intrinsic_component(instr) : 0;
reg = nir_dest_index(ctx, &instr->dest);
if (is_uniform && !ctx->is_blend) {
- emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysval_count + offset), indirect_offset, 0);
+ emit_ubo_read(ctx, &instr->instr, reg, (ctx->sysval_count + offset) * 16, indirect_offset, 4, 0);
} else if (is_ubo) {
nir_src index = instr->src[0];
- /* We don't yet support indirect UBOs. For indirect
- * block numbers (if that's possible), we don't know
- * enough about the hardware yet. For indirect sources,
- * we know what we need but we need to add some NIR
- * support for lowering correctly with respect to
- * 128-bit reads */
-
+ /* TODO: Is indirect block number possible? */
assert(nir_src_is_const(index));
- assert(nir_src_is_const(*src_offset));
-
- /* TODO: Alignment */
- assert((offset & 0xF) == 0);
uint32_t uindex = nir_src_as_uint(index) + 1;
- emit_ubo_read(ctx, &instr->instr, reg, offset / 16, NULL, uindex);
+ emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex);
} else if (is_ssbo) {
nir_src index = instr->src[0];
assert(nir_src_is_const(index));
emit_ssbo_access(ctx, &instr->instr, true, reg, offset, indirect_offset, uindex);
} else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
- emit_varying_read(ctx, reg, offset, nr_comp, component, !direct ? &instr->src[0] : NULL, t);
+ emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t, is_flat);
} else if (ctx->is_blend) {
/* For blend shaders, load the input color, which is
* preloaded to r0 */
- midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), blank_alu_src, reg);
+ midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), reg);
emit_mir_instruction(ctx, move);
- } else if (ctx->stage == MESA_SHADER_VERTEX) {
- midgard_instruction ins = m_ld_attr_32(reg, offset);
- ins.load_store.arg_1 = 0x1E;
- ins.load_store.arg_2 = 0x1E;
- ins.mask = mask_of(nr_comp);
-
- /* Use the type appropriate load */
- switch (t) {
- case nir_type_uint:
- case nir_type_bool:
- ins.load_store.op = midgard_op_ld_attr_32u;
- break;
- case nir_type_int:
- ins.load_store.op = midgard_op_ld_attr_32i;
- break;
- case nir_type_float:
- ins.load_store.op = midgard_op_ld_attr_32;
- break;
- default:
- unreachable("Attempted to load unknown type");
- break;
- }
-
- emit_mir_instruction(ctx, ins);
+ schedule_barrier(ctx);
+ } else if (ctx->stage == MESA_SHADER_VERTEX) {
+ emit_attr_read(ctx, reg, offset, nr_comp, t);
} else {
DBG("Unknown load\n");
assert(0);
break;
}
+ /* Artefact of load_interpolated_input. TODO: other barycentric modes */
+ case nir_intrinsic_load_barycentric_pixel:
+ break;
+
/* Reads 128-bit value raw off the tilebuffer during blending, tasty */
case nir_intrinsic_load_raw_output_pan:
+ case nir_intrinsic_load_output_u8_as_fp16_pan:
reg = nir_dest_index(ctx, &instr->dest);
assert(ctx->is_blend);
- midgard_instruction ins = m_ld_color_buffer_8(reg, 0);
- emit_mir_instruction(ctx, ins);
+ /* T720 and below use different blend opcodes with slightly
+ * different semantics than T760 and up */
+
+ midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
+ bool old_blend = ctx->quirks & MIDGARD_OLD_BLEND;
+
+ if (instr->intrinsic == nir_intrinsic_load_output_u8_as_fp16_pan) {
+ ld.load_store.op = old_blend ?
+ midgard_op_ld_color_buffer_u8_as_fp16_old :
+ midgard_op_ld_color_buffer_u8_as_fp16;
+
+ if (old_blend) {
+ ld.load_store.address = 1;
+ ld.load_store.arg_2 = 0x1E;
+ }
+
+ for (unsigned c = 2; c < 16; ++c)
+ ld.swizzle[0][c] = 0;
+ }
+
+ emit_mir_instruction(ctx, ld);
break;
case nir_intrinsic_load_blend_const_color_rgba: {
/* Blend constants are embedded directly in the shader and
* patched in, so we use some magic routing */
- midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, reg);
+ midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), reg);
ins.has_constants = true;
ins.has_blend_constant = true;
emit_mir_instruction(ctx, ins);
reg = nir_src_index(ctx, &instr->src[0]);
if (ctx->stage == MESA_SHADER_FRAGMENT) {
- /* Determine number of render targets */
emit_fragment_store(ctx, reg, offset);
} else if (ctx->stage == MESA_SHADER_VERTEX) {
/* We should have been vectorized, though we don't
emit_explicit_constant(ctx, reg, reg);
- unsigned component = nir_intrinsic_component(instr);
+ unsigned dst_component = nir_intrinsic_component(instr);
+ unsigned nr_comp = nir_src_num_components(instr->src[0]);
midgard_instruction st = m_st_vary_32(reg, offset);
st.load_store.arg_1 = 0x9E;
st.load_store.arg_2 = 0x1E;
- st.load_store.swizzle = SWIZZLE_XYZW << (2*component);
+
+ switch (nir_alu_type_get_base_type(nir_intrinsic_type(instr))) {
+ case nir_type_uint:
+ case nir_type_bool:
+ st.load_store.op = midgard_op_st_vary_32u;
+ break;
+ case nir_type_int:
+ st.load_store.op = midgard_op_st_vary_32i;
+ break;
+ case nir_type_float:
+ st.load_store.op = midgard_op_st_vary_32;
+ break;
+ default:
+ unreachable("Attempted to store unknown type");
+ break;
+ }
+
+ /* nir_intrinsic_component(store_intr) encodes the
+ * destination component start. Source component offset
+ * adjustment is taken care of in
+ * install_registers_instr(), when offset_swizzle() is
+ * called.
+ */
+ unsigned src_component = COMPONENT_X;
+
+ assert(nr_comp > 0);
+ for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) {
+ st.swizzle[0][i] = src_component;
+ if (i >= dst_component && i < dst_component + nr_comp - 1)
+ src_component++;
+ }
+
emit_mir_instruction(ctx, st);
} else {
DBG("Unknown store\n");
case nir_intrinsic_store_raw_output_pan:
assert (ctx->stage == MESA_SHADER_FRAGMENT);
reg = nir_src_index(ctx, &instr->src[0]);
- emit_fragment_store(ctx, reg, 0);
+
+ if (ctx->quirks & MIDGARD_OLD_BLEND) {
+ /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So
+ * reg = r0.x. We want to splatter. So we can do a 32-bit move
+ * of:
+ *
+ * imov r0.xyzw, r0.xxxx
+ */
+
+ unsigned expanded = make_compiler_temp(ctx);
+
+ midgard_instruction splatter = v_mov(reg, expanded);
+
+ for (unsigned c = 0; c < 16; ++c)
+ splatter.swizzle[1][c] = 0;
+
+ emit_mir_instruction(ctx, splatter);
+ emit_fragment_store(ctx, expanded, ctx->blend_rt);
+ } else
+ emit_fragment_store(ctx, reg, ctx->blend_rt);
break;
emit_ssbo_access(ctx, &instr->instr, false, reg, offset, indirect_offset, uindex);
break;
- case nir_intrinsic_load_alpha_ref_float:
- assert(instr->dest.is_ssa);
-
- float ref_value = ctx->alpha_ref;
-
- /* See emit_load_const */
- float *v = ralloc_array(NULL, float, 4);
- memcpy(v, &ref_value, sizeof(float));
- _mesa_hash_table_u64_insert(ctx->ssa_constants, (instr->dest.ssa.index << 1) + 1, v);
- break;
-
case nir_intrinsic_load_viewport_scale:
case nir_intrinsic_load_viewport_offset:
case nir_intrinsic_load_num_work_groups:
- emit_sysval_read(ctx, &instr->instr, -1, 3);
+ case nir_intrinsic_load_sampler_lod_parameters_pan:
+ emit_sysval_read(ctx, &instr->instr, ~0, 3);
break;
case nir_intrinsic_load_work_group_id:
emit_compute_builtin(ctx, instr);
break;
+ case nir_intrinsic_load_vertex_id:
+ case nir_intrinsic_load_instance_id:
+ emit_vertex_builtin(ctx, instr);
+ break;
+
default:
printf ("Unhandled intrinsic\n");
assert(0);
case GLSL_SAMPLER_DIM_2D:
case GLSL_SAMPLER_DIM_EXTERNAL:
+ case GLSL_SAMPLER_DIM_RECT:
return MALI_TEX_2D;
case GLSL_SAMPLER_DIM_3D:
midgard_instruction ins = {
.type = TAG_TEXTURE_4,
.mask = 0xF,
- .ssa_args = {
- .dest = nir_dest_index(ctx, &instr->dest),
- .src = { -1, -1, -1 },
- },
+ .dest = nir_dest_index(ctx, &instr->dest),
+ .src = { ~0, ~0, ~0, ~0 },
+ .swizzle = SWIZZLE_IDENTITY_4,
.texture = {
.op = midgard_texop,
.format = midgard_tex_format(instr->sampler_dim),
.texture_handle = texture_index,
.sampler_handle = sampler_index,
- .swizzle = SWIZZLE_XYZW,
- .in_reg_swizzle = SWIZZLE_XYZW,
/* TODO: half */
.in_reg_full = 1,
.out_full = 1,
.sampler_type = midgard_sampler_type(instr->dest_type),
+ .shadow = instr->is_shadow,
}
};
+ /* We may need a temporary for the coordinate */
+
+ bool needs_temp_coord =
+ (midgard_texop == TEXTURE_OP_TEXEL_FETCH) ||
+ (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) ||
+ (instr->is_shadow);
+
+ unsigned coords = needs_temp_coord ? make_compiler_temp_reg(ctx) : 0;
+
for (unsigned i = 0; i < instr->num_srcs; ++i) {
int index = nir_src_index(ctx, &instr->src[i].src);
- midgard_vector_alu_src alu_src = blank_alu_src;
+ unsigned nr_components = nir_src_num_components(instr->src[i].src);
switch (instr->src[i].src_type) {
case nir_tex_src_coord: {
emit_explicit_constant(ctx, index, index);
- /* Texelfetch coordinates uses all four elements
- * (xyz/index) regardless of texture dimensionality,
- * which means it's necessary to zero the unused
- * components to keep everything happy */
+ unsigned coord_mask = mask_of(instr->coord_components);
- if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
- unsigned old_index = index;
+ bool flip_zw = (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) && (coord_mask & (1 << COMPONENT_Z));
- index = make_compiler_temp(ctx);
-
- /* mov index, old_index */
- midgard_instruction mov = v_mov(old_index, blank_alu_src, index);
- mov.mask = 0x3;
- emit_mir_instruction(ctx, mov);
-
- /* mov index.zw, #0 */
- mov = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT),
- blank_alu_src, index);
- mov.has_constants = true;
- mov.mask = (1 << COMPONENT_Z) | (1 << COMPONENT_W);
- emit_mir_instruction(ctx, mov);
- }
+ if (flip_zw)
+ coord_mask ^= ((1 << COMPONENT_Z) | (1 << COMPONENT_W));
if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
/* texelFetch is undefined on samplerCube */
* select the face and copy the xy into the
* texture register */
- unsigned temp = make_compiler_temp(ctx);
- midgard_instruction st = m_st_cubemap_coords(temp, 0);
- st.ssa_args.src[0] = index;
- st.mask = 0x3; /* xy */
- st.load_store.arg_1 = 0x20;
- st.load_store.swizzle = alu_src.swizzle;
- emit_mir_instruction(ctx, st);
+ midgard_instruction ld = m_ld_cubemap_coords(coords, 0);
+ ld.src[1] = index;
+ ld.mask = 0x3; /* xy */
+ ld.load_store.arg_1 = 0x20;
+ ld.swizzle[1][3] = COMPONENT_X;
+ emit_mir_instruction(ctx, ld);
- ins.ssa_args.src[0] = temp;
+ /* xyzw -> xyxx */
+ ins.swizzle[1][2] = instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
+ ins.swizzle[1][3] = COMPONENT_X;
+ } else if (needs_temp_coord) {
+ /* mov coord_temp, coords */
+ midgard_instruction mov = v_mov(index, coords);
+ mov.mask = coord_mask;
+
+ if (flip_zw)
+ mov.swizzle[1][COMPONENT_W] = COMPONENT_Z;
+
+ emit_mir_instruction(ctx, mov);
} else {
- ins.ssa_args.src[0] = index;
+ coords = index;
+ }
+
+ ins.src[1] = coords;
+
+ /* Texelfetch coordinates uses all four elements
+ * (xyz/index) regardless of texture dimensionality,
+ * which means it's necessary to zero the unused
+ * components to keep everything happy */
+
+ if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
+ /* mov index.zw, #0, or generalized */
+ midgard_instruction mov =
+ v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), coords);
+ mov.has_constants = true;
+ mov.mask = coord_mask ^ 0xF;
+ emit_mir_instruction(ctx, mov);
}
if (instr->sampler_dim == GLSL_SAMPLER_DIM_2D) {
- /* Array component in w but NIR wants it in z */
- ins.texture.in_reg_swizzle = SWIZZLE_XYZZ;
+ /* Array component in w but NIR wants it in z,
+ * but if we have a temp coord we already fixed
+ * that up */
+
+ if (nr_components == 3) {
+ ins.swizzle[1][2] = COMPONENT_Z;
+ ins.swizzle[1][3] = needs_temp_coord ? COMPONENT_W : COMPONENT_Z;
+ } else if (nr_components == 2) {
+ ins.swizzle[1][2] =
+ instr->is_shadow ? COMPONENT_Z : COMPONENT_X;
+ ins.swizzle[1][3] = COMPONENT_X;
+ } else
+ unreachable("Invalid texture 2D components");
+ }
+
+ if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
+ /* We zeroed */
+ ins.swizzle[1][2] = COMPONENT_Z;
+ ins.swizzle[1][3] = COMPONENT_W;
}
break;
break;
ins.texture.lod_register = true;
- ins.ssa_args.src[1] = index;
+ ins.src[2] = index;
+
+ for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
+ ins.swizzle[2][c] = COMPONENT_X;
+
emit_explicit_constant(ctx, index, index);
break;
};
+ case nir_tex_src_offset: {
+ ins.texture.offset_register = true;
+ ins.src[3] = index;
+
+ for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c)
+ ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
+
+ emit_explicit_constant(ctx, index, index);
+ break;
+ };
+
+ case nir_tex_src_comparator: {
+ unsigned comp = COMPONENT_Z;
+
+ /* mov coord_temp.foo, coords */
+ midgard_instruction mov = v_mov(index, coords);
+ mov.mask = 1 << comp;
+
+ for (unsigned i = 0; i < MIR_VEC_COMPONENTS; ++i)
+ mov.swizzle[1][i] = COMPONENT_X;
+
+ emit_mir_instruction(ctx, mov);
+ break;
+ }
+
default:
unreachable("Unknown texture source type\n");
}
static void
emit_tex(compiler_context *ctx, nir_tex_instr *instr)
{
- /* Fixup op, since only textureLod is permitted in VS but NIR can give
- * generic tex in some cases (which confuses the hardware) */
-
- bool is_vertex = ctx->stage == MESA_SHADER_VERTEX;
-
- if (is_vertex && instr->op == nir_texop_tex)
- instr->op = nir_texop_txl;
-
switch (instr->op) {
case nir_texop_tex:
case nir_texop_txb:
emit_texop_native(ctx, instr, TEXTURE_OP_TEXEL_FETCH);
break;
case nir_texop_txs:
- emit_sysval_read(ctx, &instr->instr, -1, 4);
+ emit_sysval_read(ctx, &instr->instr, ~0, 4);
break;
default:
unreachable("Unhanlded texture op");
/* ALU instructions can inline or embed constants, which decreases register
* pressure and saves space. */
-#define CONDITIONAL_ATTACH(src) { \
- void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
+#define CONDITIONAL_ATTACH(idx) { \
+ void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[idx] + 1); \
\
if (entry) { \
- attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
- alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
+ attach_constants(ctx, alu, entry, alu->src[idx] + 1); \
+ alu->src[idx] = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
} \
}
static void
-inline_alu_constants(compiler_context *ctx)
+inline_alu_constants(compiler_context *ctx, midgard_block *block)
{
- mir_foreach_instr(ctx, alu) {
+ mir_foreach_instr_in_block(block, alu) {
/* Other instructions cannot inline constants */
if (alu->type != TAG_ALU_4) continue;
+ if (alu->compact_branch) continue;
/* If there is already a constant here, we can do nothing */
if (alu->has_constants) continue;
- CONDITIONAL_ATTACH(src[0]);
+ CONDITIONAL_ATTACH(0);
if (!alu->has_constants) {
- CONDITIONAL_ATTACH(src[1])
+ CONDITIONAL_ATTACH(1)
} else if (!alu->inline_constant) {
/* Corner case: _two_ vec4 constants, for instance with a
* csel. For this case, we can only use a constant
* to the destination register.
*/
- void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src[1] + 1);
- unsigned scratch = alu->ssa_args.dest;
+ void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->src[1] + 1);
+ unsigned scratch = alu->dest;
if (entry) {
- midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, scratch);
- attach_constants(ctx, &ins, entry, alu->ssa_args.src[1] + 1);
-
- /* Force a break XXX Defer r31 writes */
- ins.unit = UNIT_VLUT;
+ midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
+ attach_constants(ctx, &ins, entry, alu->src[1] + 1);
/* Set the source */
- alu->ssa_args.src[1] = scratch;
+ alu->src[1] = scratch;
/* Inject us -before- the last instruction which set r31 */
- mir_insert_instruction_before(mir_prev_op(alu), ins);
+ mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
}
}
}
* sometimes a performance boost */
static void
-embedded_to_inline_constant(compiler_context *ctx)
+embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
{
- mir_foreach_instr(ctx, ins) {
+ mir_foreach_instr_in_block(block, ins) {
if (!ins->has_constants) continue;
-
- if (ins->ssa_args.inline_constant) continue;
+ if (ins->has_inline_constant) continue;
/* Blend constants must not be inlined by definition */
if (ins->has_blend_constant) continue;
int op = ins->alu.op;
- if (ins->ssa_args.src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
+ if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
bool flip = alu_opcode_props[op].props & OP_COMMUTES;
switch (op) {
break;
}
- if (flip) {
- /* Flip the SSA numbers */
- ins->ssa_args.src[0] = ins->ssa_args.src[1];
- ins->ssa_args.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
-
- /* And flip the modifiers */
-
- unsigned src_temp;
-
- src_temp = ins->alu.src2;
- ins->alu.src2 = ins->alu.src1;
- ins->alu.src1 = src_temp;
- }
+ if (flip)
+ mir_flip(ins);
}
- if (ins->ssa_args.src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
+ if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
/* Extract the source information */
midgard_vector_alu_src *src;
midgard_vector_alu_src *m = (midgard_vector_alu_src *) &q;
src = m;
- /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
- int component = src->swizzle & 3;
+ /* Component is from the swizzle. Take a nonzero component */
+ assert(ins->mask);
+ unsigned first_comp = ffs(ins->mask) - 1;
+ unsigned component = ins->swizzle[1][first_comp];
/* Scale constant appropriately, if we can legally */
uint16_t scaled_constant = 0;
if (scaled_constant != iconstants[component])
continue;
} else {
- float original = (float) ins->constants[component];
+ float *f = (float *) ins->constants;
+ float original = f[component];
scaled_constant = _mesa_float_to_half(original);
/* Check for loss of precision. If this is
continue;
}
- /* Make sure that the constant is not itself a
- * vector by checking if all accessed values
- * (by the swizzle) are the same. */
+ /* Make sure that the constant is not itself a vector
+ * by checking if all accessed values are the same. */
- uint32_t *cons = (uint32_t *) ins->constants;
+ uint32_t *cons = ins->constants;
uint32_t value = cons[component];
bool is_vector = false;
unsigned mask = effective_writemask(&ins->alu, ins->mask);
- for (int c = 1; c < 4; ++c) {
+ for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
/* We only care if this component is actually used */
if (!(mask & (1 << c)))
continue;
- uint32_t test = cons[(src->swizzle >> (2 * c)) & 3];
+ uint32_t test = cons[ins->swizzle[1][c]];
if (test != value) {
is_vector = true;
/* Get rid of the embedded constant */
ins->has_constants = false;
- ins->ssa_args.src[1] = -1;
- ins->ssa_args.inline_constant = true;
+ ins->src[1] = ~0;
+ ins->has_inline_constant = true;
ins->inline_constant = scaled_constant;
}
}
mir_foreach_instr_in_block_safe(block, ins) {
if (!midgard_is_branch_unit(ins->unit)) continue;
- /* We ignore prepacked branches since the fragment epilogue is
- * just generally special */
- if (ins->prepacked_branch) continue;
-
- /* Discards are similarly special and may not correspond to the
- * end of a block */
-
- if (ins->branch.target_type == TARGET_DISCARD) continue;
-
- if (branched) {
- /* We already branched, so this is dead */
+ if (branched)
mir_remove_instruction(ins);
- }
branched = true;
}
if (ins->alu.outmod != midgard_outmod_pos) continue;
/* TODO: Registers? */
- unsigned src = ins->ssa_args.src[1];
+ unsigned src = ins->src[1];
if (src & IS_REG) continue;
- assert(!mir_has_multiple_writes(ctx, src));
/* There might be a source modifier, too */
if (mir_nontrivial_source2_mod(ins)) continue;
/* Backpropagate the modifier */
mir_foreach_instr_in_block_from_rev(block, v, mir_prev_op(ins)) {
if (v->type != TAG_ALU_4) continue;
- if (v->ssa_args.dest != src) continue;
+ if (v->dest != src) continue;
/* Can we even take a float outmod? */
if (midgard_is_integer_out_op(v->alu.op)) continue;
return progress;
}
-static void
-emit_fragment_epilogue(compiler_context *ctx)
+static unsigned
+emit_fragment_epilogue(compiler_context *ctx, unsigned rt)
{
- /* Just emit the last chunk with the branch */
- EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, -1, midgard_condition_always);
+ /* Loop to ourselves */
+
+ struct midgard_instruction ins = v_branch(false, false);
+ ins.writeout = true;
+ ins.branch.target_block = ctx->block_count - 1;
+ ins.constants[0] = rt * 0x100;
+ emit_mir_instruction(ctx, ins);
+
+ ctx->current_block->epilogue = true;
+ schedule_barrier(ctx);
+ return ins.branch.target_block;
}
static midgard_block *
ctx->after_block = NULL;
if (!this_block)
- this_block = calloc(sizeof(midgard_block), 1);
+ this_block = create_empty_block(ctx);
list_addtail(&this_block->link, &ctx->blocks);
this_block->is_scheduled = false;
++ctx->block_count;
- ctx->texture_index[0] = -1;
- ctx->texture_index[1] = -1;
-
/* Set up current block */
list_inithead(&this_block->instructions);
ctx->current_block = this_block;
++ctx->instruction_count;
}
- inline_alu_constants(ctx);
- embedded_to_inline_constant(ctx);
-
- /* Append fragment shader epilogue (value writeout) */
- if (ctx->stage == MESA_SHADER_FRAGMENT) {
- if (block == nir_impl_last_block(ctx->func->impl)) {
- emit_fragment_epilogue(ctx);
- }
- }
-
- /* Allow the next control flow to access us retroactively, for
- * branching etc */
- ctx->current_block = this_block;
-
return this_block;
}
{
midgard_block *before_block = ctx->current_block;
- /* Conditional branches expect the condition in r31.w; emit a move for
- * that in the _previous_ block (which is the current block). */
- emit_condition(ctx, &nif->condition, true, COMPONENT_X);
-
/* Speculatively emit the branch, but we can't fill it in until later */
EMIT(branch, true, true);
midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
+ then_branch->src[0] = nir_src_index(ctx, &nif->condition);
/* Emit the two subblocks. */
midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
/* Wire up the successors */
- ctx->after_block = calloc(sizeof(midgard_block), 1);
+ ctx->after_block = create_empty_block(ctx);
midgard_block_add_successor(before_block, then_block);
midgard_block_add_successor(before_block, else_block);
/* Fix up the break statements we emitted to point to the right place,
* now that we can allocate a block number for them */
- ctx->after_block = calloc(sizeof(midgard_block), 1);
+ ctx->after_block = create_empty_block(ctx);
list_for_each_entry_from(struct midgard_block, block, start_block, &ctx->blocks, link) {
mir_foreach_instr_in_block(block, ins) {
if (ins->type != TAG_ALU_4) continue;
if (!ins->compact_branch) continue;
- if (ins->prepacked_branch) continue;
/* We found a branch -- check the type to see if we need to do anything */
if (ins->branch.target_type != TARGET_BREAK) continue;
unsigned first_tag = 0;
mir_foreach_block_from(ctx, initial_block, v) {
- midgard_bundle *initial_bundle =
- util_dynarray_element(&v->bundles, midgard_bundle, 0);
+ if (v->quadword_count) {
+ midgard_bundle *initial_bundle =
+ util_dynarray_element(&v->bundles, midgard_bundle, 0);
- if (initial_bundle) {
first_tag = initial_bundle->tag;
break;
}
return first_tag;
}
+static unsigned
+pan_format_from_nir_base(nir_alu_type base)
+{
+ switch (base) {
+ case nir_type_int:
+ return MALI_FORMAT_SINT;
+ case nir_type_uint:
+ case nir_type_bool:
+ return MALI_FORMAT_UINT;
+ case nir_type_float:
+ return MALI_CHANNEL_FLOAT;
+ default:
+ unreachable("Invalid base");
+ }
+}
+
+static unsigned
+pan_format_from_nir_size(nir_alu_type base, unsigned size)
+{
+ if (base == nir_type_float) {
+ switch (size) {
+ case 16: return MALI_FORMAT_SINT;
+ case 32: return MALI_FORMAT_UNORM;
+ default:
+ unreachable("Invalid float size for format");
+ }
+ } else {
+ switch (size) {
+ case 1:
+ case 8: return MALI_CHANNEL_8;
+ case 16: return MALI_CHANNEL_16;
+ case 32: return MALI_CHANNEL_32;
+ default:
+ unreachable("Invalid int size for format");
+ }
+ }
+}
+
+static enum mali_format
+pan_format_from_glsl(const struct glsl_type *type)
+{
+ enum glsl_base_type glsl_base = glsl_get_base_type(glsl_without_array(type));
+ nir_alu_type t = nir_get_nir_type_for_glsl_base_type(glsl_base);
+
+ unsigned base = nir_alu_type_get_base_type(t);
+ unsigned size = nir_alu_type_get_type_size(t);
+
+ return pan_format_from_nir_base(base) |
+ pan_format_from_nir_size(base, size) |
+ MALI_NR_CHANNELS(4);
+}
+
+/* For each fragment writeout instruction, generate a writeout loop to
+ * associate with it */
+
+static void
+mir_add_writeout_loops(compiler_context *ctx)
+{
+ for (unsigned rt = 0; rt < ARRAY_SIZE(ctx->writeout_branch); ++rt) {
+ midgard_instruction *br = ctx->writeout_branch[rt];
+ if (!br) continue;
+
+ unsigned popped = br->branch.target_block;
+ midgard_block_add_successor(mir_get_block(ctx, popped - 1), ctx->current_block);
+ br->branch.target_block = emit_fragment_epilogue(ctx, rt);
+
+ /* If we have more RTs, we'll need to restore back after our
+ * loop terminates */
+
+ if ((rt + 1) < ARRAY_SIZE(ctx->writeout_branch) && ctx->writeout_branch[rt + 1]) {
+ midgard_instruction uncond = v_branch(false, false);
+ uncond.branch.target_block = popped;
+ emit_mir_instruction(ctx, uncond);
+ midgard_block_add_successor(ctx->current_block, mir_get_block(ctx, popped));
+ schedule_barrier(ctx);
+ } else {
+ /* We're last, so we can terminate here */
+ br->last_writeout = true;
+ }
+ }
+}
+
int
-midgard_compile_shader_nir(struct midgard_screen *screen, nir_shader *nir, midgard_program *program, bool is_blend)
+midgard_compile_shader_nir(nir_shader *nir, midgard_program *program, bool is_blend, unsigned blend_rt, unsigned gpu_id, bool shaderdb)
{
struct util_dynarray *compiled = &program->compiled;
midgard_debug = debug_get_option_midgard_debug();
- compiler_context ictx = {
- .nir = nir,
- .screen = screen,
- .stage = nir->info.stage,
- .temp_alloc = 0,
+ /* TODO: Bound against what? */
+ compiler_context *ctx = rzalloc(NULL, compiler_context);
- .is_blend = is_blend,
- .blend_constant_offset = 0,
-
- .alpha_ref = program->alpha_ref
- };
-
- compiler_context *ctx = &ictx;
+ ctx->nir = nir;
+ ctx->stage = nir->info.stage;
+ ctx->is_blend = is_blend;
+ ctx->alpha_ref = program->alpha_ref;
+ ctx->blend_rt = blend_rt;
+ ctx->quirks = midgard_get_quirks(gpu_id);
/* Start off with a safe cutoff, allowing usage of all 16 work
* registers. Later, we'll promote uniform reads to uniform registers
for (int c = 0; c < sz; ++c) {
program->varyings[loc + c] = var->data.location + c;
+ program->varying_type[loc + c] = pan_format_from_glsl(var->type);
max_varying = MAX2(max_varying, loc + c);
}
}
if (ctx->stage == MESA_SHADER_VERTEX) {
NIR_PASS_V(nir, nir_lower_viewport_transform);
- NIR_PASS_V(nir, nir_clamp_psiz, 1.0, 1024.0);
+ NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
}
NIR_PASS_V(nir, nir_lower_var_copies);
/* Optimisation passes */
- optimise_nir(nir);
+ optimise_nir(nir, ctx->quirks);
if (midgard_debug & MIDGARD_DBG_SHADERS) {
nir_print_shader(nir, stdout);
ctx->func = func;
emit_cf_list(ctx, &func->impl->body);
- emit_block(ctx, func->impl->end_block);
-
break; /* TODO: Multi-function shaders */
}
util_dynarray_init(compiled, NULL);
+ /* Per-block lowering before opts */
+
+ mir_foreach_block(ctx, block) {
+ inline_alu_constants(ctx, block);
+ midgard_opt_promote_fmov(ctx, block);
+ embedded_to_inline_constant(ctx, block);
+ }
/* MIR-level optimizations */
bool progress = false;
progress |= midgard_opt_not_propagate(ctx, block);
progress |= midgard_opt_fuse_src_invert(ctx, block);
progress |= midgard_opt_fuse_dest_invert(ctx, block);
+ progress |= midgard_opt_csel_invert(ctx, block);
+ progress |= midgard_opt_drop_cmp_invert(ctx, block);
+ progress |= midgard_opt_invert_branch(ctx, block);
}
} while (progress);
assert(!ins->invert);
}
+ if (ctx->stage == MESA_SHADER_FRAGMENT)
+ mir_add_writeout_loops(ctx);
+
/* Schedule! */
- schedule_program(ctx);
+ midgard_schedule_program(ctx);
+ mir_ra(ctx);
/* Now that all the bundles are scheduled and we can calculate block
* sizes, emit actual branch instructions rather than placeholders */
if (!midgard_is_branch_unit(ins->unit)) continue;
- if (ins->prepacked_branch) continue;
-
/* Parse some basic branch info */
bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
bool is_conditional = ins->branch.conditional;
bool is_inverted = ins->branch.invert_conditional;
bool is_discard = ins->branch.target_type == TARGET_DISCARD;
+ bool is_writeout = ins->writeout;
/* Determine the block we're jumping to */
int target_number = ins->branch.target_block;
midgard_jmp_writeout_op op =
is_discard ? midgard_jmp_writeout_op_discard :
+ is_writeout ? midgard_jmp_writeout_op_writeout :
(is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
midgard_jmp_writeout_op_branch_cond;
/* Midgard prefetches instruction types, so during emission we
* need to lookahead. Unless this is the last instruction, in
- * which we return 1. Or if this is the second to last and the
- * last is an ALU, then it's also 1... */
+ * which we return 1. */
mir_foreach_block(ctx, block) {
mir_foreach_bundle_in_block(block, bundle) {
int lookahead = 1;
- if (current_bundle + 1 < bundle_count) {
- uint8_t next = source_order_bundles[current_bundle + 1]->tag;
-
- if (!(current_bundle + 2 < bundle_count) && IS_ALU(next)) {
- lookahead = 1;
- } else {
- lookahead = next;
- }
- }
+ if (!bundle->last_writeout && (current_bundle + 1 < bundle_count))
+ lookahead = source_order_bundles[current_bundle + 1]->tag;
emit_binary_bundle(ctx, bundle, compiled, lookahead);
++current_bundle;
program->tls_size = ctx->tls_size;
if (midgard_debug & MIDGARD_DBG_SHADERS)
- disassemble_midgard(program->compiled.data, program->compiled.size, false, 0, "");
+ disassemble_midgard(program->compiled.data, program->compiled.size, gpu_id, ctx->stage);
- if (midgard_debug & MIDGARD_DBG_SHADERDB) {
- unsigned nr_bundles = 0, nr_ins = 0, nr_quadwords = 0;
+ if (midgard_debug & MIDGARD_DBG_SHADERDB || shaderdb) {
+ unsigned nr_bundles = 0, nr_ins = 0;
/* Count instructions and bundles */
- mir_foreach_instr_global(ctx, ins) {
- nr_ins++;
- }
-
mir_foreach_block(ctx, block) {
nr_bundles += util_dynarray_num_elements(
&block->bundles, midgard_bundle);
- nr_quadwords += block->quadword_count;
+ mir_foreach_bundle_in_block(block, bun)
+ nr_ins += bun->instruction_count;
}
/* Calculate thread count. There are certain cutoffs by
fprintf(stderr, "shader%d - %s shader: "
"%u inst, %u bundles, %u quadwords, "
"%u registers, %u threads, %u loops, "
- "%d:%d spills:fills\n",
+ "%u:%u spills:fills\n",
SHADER_DB_COUNT++,
gl_shader_stage_name(ctx->stage),
- nr_ins, nr_bundles, nr_quadwords,
+ nr_ins, nr_bundles, ctx->quadword_count,
nr_registers, nr_threads,
ctx->loop_count,
ctx->spills, ctx->fills);
}
+ ralloc_free(ctx);
return 0;
}
projects / mesa.git / blobdiff