pan/mdg: Implement raw colourbuf loads on T720

[mesa.git] / src / panfrost / midgard / midgard_compile.c

diff --git a/src/panfrost/midgard/midgard_compile.c b/src/panfrost/midgard/midgard_compile.c
index 643fe114b0da9438fe74e9d304b396841fe822bc..e1d6cac7672f55593addc471f6b1b4e3a9abdd95 100644 (file)
--- a/src/panfrost/midgard/midgard_compile.c
+++ b/src/panfrost/midgard/midgard_compile.c
@@ -383,6 +383,8 @@ optimise_nir(nir_shader *nir, unsigned quirks)
         if (quirks & MIDGARD_BROKEN_LOD)
                 NIR_PASS_V(nir, midgard_nir_lod_errata);
 
+        NIR_PASS(progress, nir, midgard_nir_lower_algebraic_early);
+
         do {
                 progress = false;
 
@@ -578,13 +580,23 @@ reg_mode_for_nir(nir_alu_instr *instr)
         case nir_op_fexp2:
         case nir_op_flog2:
                 max_bitsize = MAX2(max_bitsize, 32);
+                break;
+
+        /* These get lowered to moves */
+        case nir_op_pack_32_4x8:
+                max_bitsize = 8;
+                break;
+        case nir_op_pack_32_2x16:
+                max_bitsize = 16;
+                break;
         default:
                 break;
         }
 
+
         switch (max_bitsize) {
+                /* Use 16 pipe for 8 since we don't support vec16 yet */
         case 8:
-                return midgard_reg_mode_8;
         case 16:
                 return midgard_reg_mode_16;
         case 32:
@@ -909,6 +921,14 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
                 break;
         }
 
+        case nir_op_unpack_32_2x16:
+        case nir_op_unpack_32_4x8:
+        case nir_op_pack_32_2x16:
+        case nir_op_pack_32_4x8: {
+                op = midgard_alu_op_imov;
+                break;
+        }
+
         default:
                 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
                 assert(0);
@@ -1076,6 +1096,22 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
 
                 for (unsigned c = 0; c < 16; ++c)
                         ins.swizzle[1][c] = 0;
+        } else if (instr->op == nir_op_pack_32_2x16) {
+                ins.dest_type = nir_type_uint16;
+                ins.mask = mask_of(nr_components * 2);
+                ins.is_pack = true;
+        } else if (instr->op == nir_op_pack_32_4x8) {
+                ins.dest_type = nir_type_uint8;
+                ins.mask = mask_of(nr_components * 4);
+                ins.is_pack = true;
+        } else if (instr->op == nir_op_unpack_32_2x16) {
+                ins.dest_type = nir_type_uint32;
+                ins.mask = mask_of(nr_components >> 1);
+                ins.is_pack = true;
+        } else if (instr->op == nir_op_unpack_32_4x8) {
+                ins.dest_type = nir_type_uint32;
+                ins.mask = mask_of(nr_components >> 2);
+                ins.is_pack = true;
         }
 
         /* Arrange for creation of iandnot/iornot */
@@ -1135,9 +1171,7 @@ mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
         /* Once we have the NIR mask, we need to normalize to work in 32-bit space */
         unsigned bytemask = pan_to_bytemask(dsize, nir_mask);
         mir_set_bytemask(ins, bytemask);
-
-        if (dsize == 64)
-                ins->load_64 = true;
+        ins->dest_type = nir_type_uint | dsize;
 }
 
 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
@@ -1390,6 +1424,7 @@ emit_control_barrier(compiler_context *ctx)
 {
         midgard_instruction ins = {
                 .type = TAG_TEXTURE_4,
+                .dest = ~0,
                 .src = { ~0, ~0, ~0, ~0 },
                 .texture = {
                         .op = TEXTURE_OP_BARRIER,
@@ -1543,18 +1578,22 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
 
                 if (instr->intrinsic == nir_intrinsic_load_output_u8_as_fp16_pan) {
                         ld.load_store.op = old_blend ?
-                                midgard_op_ld_color_buffer_u8_as_fp16_old :
-                                midgard_op_ld_color_buffer_u8_as_fp16;
-
-                        if (old_blend) {
-                                ld.load_store.address = 1;
-                                ld.load_store.arg_2 = 0x1E;
-                        }
+                                midgard_op_ld_color_buffer_as_fp16_old :
+                                midgard_op_ld_color_buffer_as_fp16;
 
                         for (unsigned c = 4; c < 16; ++c)
                                 ld.swizzle[0][c] = 0;
 
                         ld.dest_type = nir_type_float16;
+
+                        if (old_blend) {
+                                ld.load_store.address = 1;
+                                ld.load_store.arg_2 = 0x1E;
+                        }
+                } else if (old_blend) {
+                        ld.load_store.op = midgard_op_ld_color_buffer_32u_old;
+                        ld.load_store.address = 16;
+                        ld.load_store.arg_2 = 0x1E;
                 }
 
                 emit_mir_instruction(ctx, ld);
@@ -1773,7 +1812,7 @@ midgard_tex_format(enum glsl_sampler_dim dim)
         }
 }
 
-/* Tries to attach an explicit LOD / bias as a constant. Returns whether this
+/* Tries to attach an explicit LOD or bias as a constant. Returns whether this
  * was successful */
 
 static bool