util: Add a mapping from VkFormat to PIPE_FORMAT.

[mesa.git] / src / panfrost / midgard / midgard_compile.h

diff --git a/src/panfrost/midgard/midgard_compile.h b/src/panfrost/midgard/midgard_compile.h
index b6cd2affe724b9a28cf06e57bb04b420bdf412dc..045837a7b5d98e54ec29b5037261dfb87903103b 100644 (file)
--- a/src/panfrost/midgard/midgard_compile.h
+++ b/src/panfrost/midgard/midgard_compile.h
@@ -26,26 +26,6 @@
 
 #include "compiler/nir/nir.h"
 #include "util/u_dynarray.h"
-#include "util/register_allocate.h"
-
-/* To be shoved inside panfrost_screen for the Gallium driver, or somewhere
- * else for Vulkan/standalone. The single compiler "screen" to be shared across
- * all shader compiles, used to store complex initialization (for instance,
- * related to register allocation) */
-
-struct midgard_screen {
-        /* Precomputed register allocation sets for varying numbers of work
-         * registers.  The zeroeth entry corresponds to 8 work registers. The
-         * eighth entry corresponds to 16 work registers. NULL if this set has
-         * not been allocated yet. */
-
-        struct ra_regs *regs[9];
-
-        /* Work register classes corresponds to the above register
-         * sets. 12 per set for 4 classes per work/ldst/tex */
-
-        unsigned reg_classes[9][12];
-};
 
 /* Define the general compiler entry point */
 
@@ -65,6 +45,8 @@ enum {
         PAN_SYSVAL_VIEWPORT_SCALE = 1,
         PAN_SYSVAL_VIEWPORT_OFFSET = 2,
         PAN_SYSVAL_TEXTURE_SIZE = 3,
+        PAN_SYSVAL_SSBO = 4,
+        PAN_SYSVAL_NUM_WORK_GROUPS = 5,
 } pan_sysval;
 
 #define PAN_TXS_SYSVAL_ID(texidx, dim, is_array)          \
@@ -108,7 +90,7 @@ typedef struct {
 } midgard_program;
 
 int
-midgard_compile_shader_nir(struct midgard_screen *screen, nir_shader *nir, midgard_program *program, bool is_blend);
+midgard_compile_shader_nir(nir_shader *nir, midgard_program *program, bool is_blend, unsigned gpu_id);
 
 /* NIR options are shared between the standalone compiler and the online
  * compiler. Defining it here is the simplest, though maybe not the Right
@@ -127,6 +109,7 @@ static const nir_shader_compiler_options midgard_nir_options = {
         .lower_isign = true,
         .lower_fpow = true,
         .lower_find_lsb = true,
+        .lower_fdph = true,
 
         .lower_wpos_pntc = true,